U-boot axi ethernet

Introduction

The AXI Ethernet Subsystem provides a control interface to internal registers via a 32-bit AXI4-Lite Interface subset. This AXI4-Lite slave interface supports single beat read and write data transfers (no burst transfers). The transmit and receive data interface is via the AXI4-Stream interface.

Configuration

CONFIG_DM_ETH=y
CONFIG_XILINX_AXIEMAC=y

Device tree

axi_ethernet_0: ethernet@40c00000 {
	axistream-connected = <&axi_ethernet_0_dma>;
	clock-frequency = <100000000>;
	compatible = "xlnx,axi-ethernet-7.1", "xlnx,axi-ethernet-1.00.a";
	device_type = "network";
	phy-handle = <&phy1>;
	phy-mode = "sgmii";
    reg = <0x40c00000 0x10000>;
    axi_ethernet_0_mdio: mdio {
    	#address-cells = <1>;
    	#size-cells = <0>;
		phy1: phy@1 {
			device_type = "ethernet-phy";
			reg = <1>;
		};
	};
};

Test procedure

U-Boot 2019.01 (Jul 03 2019 - 12:37:22 +0000)

Model: Xilinx MicroBlaze
DRAM:  2 GiB
Loading Environment from SPI Flash... SF: Detected n25q1024a with page size 256 Bytes, erase size 4 KiB, total 128 MiB
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Model: Xilinx MicroBlaze
Watchdog: Not found!
Net:   AXI EMAC: 40c00000, phyaddr 3, interface sgmii
eth0: ethernet@40c00000
U-BOOT for xilinx-vcu118-2019_1

ethernet@40c00000 Waiting for PHY auto negotiation to complete...... done
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
DHCP client bound to address 10.10.70.1 (1255 ms)
Hit any key to stop autoboot:  0
U-Boot>mii info
PHY 0x00: OUI = 0x5D03, Model = 0x00, Rev = 0x00, 1000baseX, HDX
PHY 0x01: OUI = 0x5D03, Model = 0x00, Rev = 0x00, 1000baseX, HDX
PHY 0x03: OUI = 0x80028, Model = 0x23, Rev = 0x01, 1000baseT, FDX
U-Boot>mii device
MII devices: 'eth0'
Current device: 'eth0'
U-Boot>dhcp
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
DHCP client bound to address 10.10.70.1 (1254 ms)
U-Boot>ping 10.10.70.101
Using ethernet@40c00000 device
host 10.10.70.101 is alive
U-Boot>

Features

  • 10/100/1000 Mbps support
  • Support for several PHY interfaces
  • Media Independent Interface Management access to PHY
  • Full Duplex support