This page provides details for using the U-Boot FPGA Driver for programming the Programmable Logic (PL) from U-boot for Zynq-7000 and Zynq UltraScale+ MPSoC. 

Table of Contents

U-Boot Configuration

For ZynqMP

For Zynq

Device tree

Not required

Test Procedure

These examples rely on a bitstream that's been converted from a *.bit to a *.bin using the Bootgen utility.  Below is a simple example of doing this for a non-secure bitstream.  For secure bitstreams the examples below provide comments regarding the contents of the required *.bif file that's supplied to Bootgen.

where -arch can specify one of <zynq | zynqmp | versal> for Zynq-7000, ZynqUS+, and Versal, respectively.  This will generate a download.bit.bin file is the present directory.  For additional details refer to the Bootgen User Guide.

The resulting *.bif file should look like:

Loading of the *.bin bitstream file can then be tested as follows.

Features

• Full Bitstream loading.
• Encrypted and Authenticated Full Bitstream loading.
• Readback of Bitstream(Configuration Data)
• PCAP status available through 'info' sub-command provides information about the state of bitstream programming.
• Bitstream loading is implemented as a blocking call to ensure completion of loading if the command returns without error.
  • Relevant commit for ZynqUS+ (as of Xilinx release 2018.1): c055151