This page provides details for using the U-Boot FPGA Driver for programming the Programmable Logic (PL) from U-boot for Zynq-7000 and Zynq UltraScale+ MPSoC.

U-Boot Configuration

For ZynqMP

CONFIG_FPGA=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y

CONFIG_CMD_FPGA=y				//Supports FPGA command.
CONFIG_CMD_FPGA_LOADP=y			//Supports loading a partial bitstream.
CONFIG_CMD_FPGA_LOADBP=y		//Supports loading a partial bitstream from a bitstream buffer.
CONFIG_CMD_FPGA_LOADFS=y		//Supports loading a bitstream from a FAT filesystem.
CONFIG_CMD_FPGA_LOADMK=y		//Supports loading a bitstream from a image generated by mkimage.
CONFIG_CMD_FPGA_LOAD_SECURE=y	//Supports loading secure bitstream.

For Zynq

CONFIG_FPGA=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y

CONFIG_CMD_FPGA=y				//Supports FPGA command.
CONFIG_CMD_FPGA_LOADP=y			//Supports loading a partial bitstream.
CONFIG_CMD_FPGA_LOADBP=y		//Supports loading a partial bitstream from a bitstream buffer.
CONFIG_CMD_FPGA_LOADFS=y		//Supports loading a bitstream from a FAT filesystem.
CONFIG_CMD_FPGA_LOADMK=y		//Supports loading a bitstream from a image generated by mkimage.
CONFIG_CMD_FPGA_LOAD_SECURE=y	//Supports loading secure bitstream.

Device tree

Not required

Test Procedure

These examples rely on a bitstream that's been converted from a *.bit to a *.bin using the Bootgen utility. Below is a simple example of doing this for a non-secure bitstream. For secure bitstreams the examples below provide comments regarding the contents of the required *.bif file that's supplied to Bootgen.

$ echo "all:
> {
>  download.bit
> }" > bit2bin.bif
$ bootgen -image bit2bin.bif -arch zynqmp -process_bitstream bin

where -arch can specify one of <zynq | zynqmp | versal> for Zynq-7000, ZynqUS+, and Versal, respectively. This will generate a download.bit.bin file is the present directory. For additional details refer to the Bootgen User Guide.

The resulting *.bif file should look like:

all:
{
 design_1_wrapper.bit
}

Loading of the *.bin bitstream file can then be tested as follows.

ZynqMP> fpga info
Xilinx Device
Descriptor @ 0x000000007ffba260
Family:         ZynqMP PL
Interface type: csu_dma configuration interface (ZynqMP)
Device Size:    1 bytes
Cookie:         0x0 (0)
Device name:    zu9eg
Device Function Table @ 0x000000007ff975e8
PCAP status     0xa02

// Non secure bit-stream loading

tftpb 0x10000000 fpga.bin
fpga load 0 0x10000000 ${filesize}

//Secure bit-stream loading

//Encrypted bit-stream with device key
//arch = zynqmp; split = false; format = BIN the_ROM_image:
//{  
//[aeskeyfile]bbram.nky  
//[keysrc_encryption]bbram_red_key  [encryption = aes, destination_device = pl] download.bit
//}
tftpb 0x10000000 fpga.bin
fpga loads 0 0x10000000 ${filesize} 2 0

//Authenticated bit-stream
//arch = zynqmp; split = false; format = BIN the_ROM_image:
//{  
//[pskfile] psk0.pem  
//[sskfile] ssk0.pem  
//[auth_params] ppk_select = 0  
//[fsbl_config]bh_auth_enable  
//[authentication = rsa, destination_device = pl] download.bit
//}
tftpb 0x10000000 fpga.bin
fpga loads 0 0x10000000 ${filesize} 0 2

Features

Full Bitstream loading.
Encrypted and Authenticated Full Bitstream loading.
Readback of Bitstream(Configuration Data)
PCAP status available through 'info' sub-command provides information about the state of bitstream programming.
Bitstream loading is implemented as a blocking call to ensure completion of loading if the command returns without error.
- Relevant commit for ZynqUS+ (as of Xilinx release 2018.1): c055151

U-Boot FPGA Driver