This wiki page complements XAPP1159. 

Table of Contents

1 Introduction

This tutorial shows how to develop a Partial Reconfiguration (PR) design for the Zynq-7000 SoC using the Xilinx Platform Studio (XPS), Software Development Kit (SDK), and PlanAhead design tools. It complements application note XAPP1159 which focuses on conceptual aspects of the PR flow and Zynq architecture specific design considerations.

1.1 Design Overview

The PR reference design is built on top of the ZC702 Base Targeted Reference Design (TRD) , an embedded video processing application that demonstrates how it is best to separate control and data processing functions. In this example a compute-intensive video filtering algorithm is moved from the Processing System (PS) onto a hardware accelerator in Programmable Logic (PL). The video filter IP core demonstrated in the ZC702 Base TRD is a Sobel filter configured with edge detection coefficients which has been generated using the High-Level Synthesis tool Vivado HLS. For this reference design, a second video filter IP core (Sepia filter) was generated again using Vivado HLS. The provided reference design demonstrates how to use software-controlled Partial Reconfiguration (PR) to dynamically reconfigure part of the PL with the desired video filter IP core and observe the video output on a monitor.

1.2 Requirements

Software

• ISE Design Suite v14.4 Embedded or System Edition

• Vivado HLS v2012.4 to generate video filter IP cores (optional).

• Silicon Labs CP210x USB to UART Bridge VCP Driver (only required when using standalone boot image).

• Terminal emulator software, for example TeraTerm (only required when using standalone boot image).

• Linux development PC with the ARM GNU cross compile tool chain and the Git tool installed (only required for completing Sections 5 and 6.5).

Hardware

• ZC702 Evaluation Kit to run the PR reference design in hardware.

• Monitor with HDMI or DVI port that supports 1080p60 video resolution.

• Avnet FMC-IMAGEON module and external video source that provides 1080p60 video input over HDMI (optional).

• USB hub, USB mouse, and USB keyboard (only required when using Linux boot image).

Licensing

• Xilinx Vivado HLS: A 30-day evaluation license can be generated after registering a Xilinx account.

• Xilinx ISE Design Suite System Edition: A 30-day evaluation license can be generated after registering a Xilinx account.

• Xilinx Partial Reconfiguration is a product inside the ISE Design Suite that requires a license. 30-day evaluation licenses are available through the Xilinx University Program (XUP).

• Xilinx IP evaluation licenses for the Video Timing Controller and Chroma Resampler IP cores can be ordered online.

• Xylon logiCVC-ML is shipped as evaluation IP core that does not require a license. License options are listed on the Xylon logiCVC-ML product site.
  Note: The provided logiCVC evaluation IP core has a 1 hour timeout built-in such that the display freezes after the timer expires. The pre-generated netlists are built from this evaluation IP core so the user can implement the design without having to purchase a license. The pre-built bitfiles and boot images are built from a full logiCVC IP core and don't expire.

1.3 Directory Structure

Download and unzip the reference design archive file xapp1159.zip to a local directory. The directory structure is:

• zc702_pr_rd -- Top-level directory

  • doc -- Readme file

  • hw -- Hardware sources

    • base_trd_prj -- Pre-configured Base TRD PlanAhead project

    • hls_sepia_prj -- Sepia filter Vivado HLS project

    • hls_sobel_prj -- Sobel filter Vivado HLS project

    • pr_prj -- Pre-configured PR PlanAhead project

  • sd -- SD card images

    • linux -- Linux boot image, kernel, devicetree, ramdisk, executables, partial binaries

    • standalone -- Standalone boot image, partial binaries

  • sw -- Software sources

    • boot -- Zynq boot image sources

      • linux -- Linux boot image sources

      • standalone -- Standalone boot image sources

    • patch -- Linux kernel patch

    • repo -- SDK standalone user repository

      • drivers -- SDK standalone user drivers

      • sw_services -- SDK standalone user software services

    • workspace -- SDK workspace/projects

      • filter_cmd -- Linux command line software application

      • filter_qt -- Linux Qt-GUI software application

      • filter_std -- Standalone software application

      • hw_platform -- Hardware platform information

      • standalone_bsp -- Bare-metal board support package

      • zynq_fsbl -- First stage boot loader

1.4 Known Issues

License error when using pre-synthesized logiCVC netlist

The provided pre-synthesized netlist for the logiCVC IP core (zc702_pr_rd/hw/pr_prj/zynq_pr_rd.srcs/sources_1/system_logicvc_0_wrapper.ngc) was generated from the full license core. Unless you posses a full license for this core, your implementation run will error out with the following message:

[Netlist 29-57] IP License required for netlist cell 'system_logicvc_0_wrapper', instantiated as 'system_i/LOGICVC_0'.
WARNING:Security:141 - No 'Source' license available for 'ip_xap_349logicvcml_TDP' version '1.0' (-5).
WARNING:Security:141 - No 'Bought' license available for 'ip_xap_349logicvcml_TDP' version '1.0' (-5).
WARNING:Security:141 - No 'Hardware_Evaluation' license available for 'ip_xap_349logicvcml_TDP' version '1.0' (-5).
WARNING:Security:141 - No 'Design_Linking' license available for 'ip_xap_349logicvcml_TDP' version '1.0' (-5).
ERROR:Security:142 - No IP Core license of type 'Design_Linking' or greater available for 'ip_xap_349logicvcml' version '1.0'.

Please replace the netlist with the one attached or run Section 3 first followed by Sections 4.1 through 4.9. In Section 3 you will generate a netlist from the evaluation logiCVC pcore which you will then import into the PlanAhead PR project in Section 4.1.

Open

Image tearing

Occasional horizontal image tearing can be observed when the sobel or sepia filter engines are enabled.

2 Vivado HLS Flow

Vivado HLS provides a tool and methodology for migrating algorithms coded in C, C++ or System-C from the Zynq PS onto the PL by generating RTL code. The Sobel filter IP core used in the Zynq Base TRD was generated using this approach. Similarly, the Sepia filter IP core can be generated based on the provided C-algorithm and Vivado HLS project. The following tutorial is based on XAPP890 and shows how to implement the Sobel filter HLS project -- the same methodology can be used for the Sepia filter HLS project.

Shortcut: Pre-generated Sobel and Sepia filter IP cores are available at zc702_pr_rd/hw/base_trd_prj/zynq_base_trd.srcs/sources_1/edk/xps_proj/pcores/sepia_filter_top_v1_04_a and zc702_pr_rd/hw/base_trd_prj/zynq_base_trd.srcs/sources_1/edk/xps_proj/pcores/sobel_filter_top_v1_04_a.

2.1 Synthesizing the HLS Design

Tutorial

1. To open Vivado HLS, select Start > All Programs > Xilinx Design Tools > Vivado 2012.4 > Vivado HLS.

2. On the Vivado HLS welcome screen, click Open Project under the Getting Started group.

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3. In the Open Project dialog, browse to the zc702_pr_rd/hw/hls_sobel_prj/sobel directory and click OK.

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4. From the icon bar, click the Synthesis button to generate the RTL for the algorithm.

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2.2 Exporting the RTL as EDK Pcore

Tutorial

1. Click the Export RTL button to package the RTL as EDK Pcore.

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2. In the dialog box, select Pcore for EDK.

3. Click the Configuration... button.

4. Enter 1.04.a for the pcore Version and confirm with OK twice.

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5. The Pcore is located in the directory zc702_pr_rd/hw/hls_sobel_prj/sobel/solution1/impl/pcores.

Repeat Sections 2.1 and 2.2 for the Sepia filter HLS project located at zc702_pr_rd/hw/hls_sepia_prj.

3 PlanAhead Base TRD Flow

The Base TRD hardware design is a PlanAhead project with an embedded XPS project. The default video filter used in the design is a Sobel filter. First you will synthesize the Base TRD with the Sobel filter using PlanAhead. Then, you will replace the Sobel filter with a Sepia filter in XPS and re-run synthesis. The generated netlists will be used as starting point for the PlanAhead PR project (see Section 4). Finally, you will export the hardware platform information so it can be imported into SDK at a later point (see Section 6.1).

Shortcut: Pre-generated netlists are available inside the PlanAhead PR project zc702_pr_rd/hw/pr_prj. A pre-configured Hardware Platform Specification is available at zc702_pr_rd/sw/workspace/hw_platform.

3.1 Synthesizing the Design

Tutorial

1. To open PlanAhead, select Start > All Programs > Xilinx Design Tools > ISE Design Suite 14.4 > PlanAhead > PlanAhead.

2. On the PlanAhead welcome screen, click Open Project under the Getting Started group.

   Open

   

3. In the Open Project dialog, select the zynq_base_trd.ppr project file.

4. Click OK.

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5. In the Design Runs window at the bottom, right-click synth_1 and select Launch Runs....

6. Click OK in Launch Selected Runs dialog.

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7. Click Cancel in the Synthesis Completed dialog.

8. Browse to the zc702_pr_rd/hw/base_trd_prj/zynq_base_trd.srcs/sources_1/edk/xps_proj/implementation directory and rename the file system_filter_engine_wrapper.ngc to system_filter_sobel_wrapper.ngc.

3.2 Replacing the Filter and Re-Synthesizing the Design

Tutorial

1. Double-click the system_i - system (system.xmp) file in the Sources tab of Project Manager to open the embedded XPS project.

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2. In XPS, select the Project tab on the left and double-click MHS File: system.mhs.

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3. Scroll down or search for sobel_filter_top and replace with sepia_filter_top.

4. From the menu bar, select File > Save and click Reload when prompted to reload the project.

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5. Close XPS and click Yes when prompted to continue to exit XPS.

6. Back in PlanAhead, select the Design Runs tab at the bottom.
   Note: The synth_1 run has a yellow exclamation mark sign on top of a green check mark next to it, indicating that the synthesis run is completed but out-of-date. This is because we have modified the XPS project by replacing the Sobel Filter with a Sepia filter.

7. Right-click synth_1 and select Launch Runs....

8. Click OK twice.

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9. Click Cancel in the Synthesis Completed dialog.

10. Browse to the zc702_pr_rd/hw/base_trd_prj/zynq_base_trd.srcs/sources_1/edk/xps_proj/implementation directory and rename the file system_filter_engine_wrapper.ngc to system_filter_sepia_wrapper.ngc.

3.3 Exporting the Hardware Platform Specification

Tutorial

1. From the menu bar, select File > Export > Export Hardware for SDK...

2. Click OK.

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3. The generated Hardware Platform Specification is located at zc702_pr_rd/hw/base_trd_prj/zynq_base_trd.sdk/SDK/SDK_Export/hw

4 PlanAhead Partial Reconfiguration Design Flow

Based on the synthesized netlists from the Base TRD hardware design, you will use the PlanAhead tool to create a reconfigurable partition, floorplan the design, add reconfigurable modules, run the implementation tools, and generate full and partial bitstreams. The promgen tool is used to convert the partial bitstreams to binary format so they can be used by the software application to configure the PL through the PCAP port.

Shortcut 1: A pre-built full bitstream (sobel configuration) is available at zc702_pr_rd/sw/boot/*/sobel.bit. Partial Sobel and Sepia bitstreams are available at zc702_pr_rd/sd/*/sobel.bin and zc702_pr_rd/sd/*/sepia.bin.

Shortcut 2: A pre-configured PlanAhead PR project is available at zc702_pr_rd/hw/pr_prj. When using this project, only the last two steps in the PR flow -- implementation and bitstream generation -- need to be run (see tutorial below).

Tutorial

1. To open PlanAhead, select Start > All Programs > Xilinx Design Tools > ISE Design Suite 14.4 > PlanAhead > PlanAhead.

2. On the PlanAhead welcome screen, click Open Project under the Getting Started group.

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3. In the Open Project dialog, browse to the zc702_pr_rd/hw/pr_prj directory and select zynq_pr_rd.ppr.

4. Click OK.

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5. In the Design Runs window at the bottom, right-click sobel and select Launch Run....

6. Click OK in the Launch Selected Runs dialog.

7. Click OK in the Launch Runs Critical Messages dialog to ignore the warnings.

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8. In the Implementation Completed dialog, select Promote Partitions.

9. Click OK twice.

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10. Click OK in the Promote Partitions dialog.

11. Click OK in the Critical Messages dialog.

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12. Select the sobel run, right-click and select Generate Bitstream.

13. Click OK.

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14. Repeat steps 5 through 13 for the sepia run, except in the Implementation Completed dialog, click Cancel.

15. Select the Tcl Console tab at the bottom.

16. At the command line prompt, enter exec promgen -b -w -p bin -data_width 32 -u 0 zynq_pr_rd.runs/sobel/sobel_system_i_FILTER_ENGINE_sobel_partial.bit -o zynq_pr_rd.runs/sobel/sobel.bin to convert the partial sobel bitfile to binary format.

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17. Next, enter exec promgen -b -w -p bin -data_width 32 -u 0 zynq_pr_rd.runs/sepia/sepia_system_i_FILTER_ENGINE_sepia_partial.bit -o zynq_pr_rd.runs/sepia/sepia.bin to convert the partial sepia bitfile to binary format.

18. Note down the size of the generated partial binary files as indicated by the promgen console output -- the file size should be identical for both partial binaries.

Alternatively, complete Sections 4.1 through 4.9 for the full PR design flow tutorial.

4.1 Creating a PR Project and Importing the Generated Netlists

Tutorial

1. Create a new directory zc702_pr_rd/hw/pr_prj_lab for this tutorial.

2. To open PlanAhead, select Start > All Programs > Xilinx Design Tools > ISE Design Suite 14.4 > PlanAhead > PlanAhead.

3. On the PlanAhead welcome screen, click Create New Project under the Getting Started group.

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4. Click Next.

5. In the Project Name dialog, change the Project name to zynq_pr_rd.

6. Browse to the zc702_pr_rd/hw/pr_prj_lab directory for Project location and click Select.

7. Click Next.

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8. In the Project Type dialog, select Post-synthesis Project and check the Enable Partial Reconfiguration box.

9. Click Next.

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10. In the Add Netlist Sources dialog, click the Add Files... button.

11. Browse to the zc702_pr_rd/hw/base_trd_prj/zynq_base_trd.srcs/sources_1/edk/xps_proj/implementation directory.

12. Select all .ngc files except for system_filter_sepia_wrapper.ngc and system_filter_sobel_wrapper.ngc and click OK.

13. Click the Add Files... button again.

14. Browse to the zc702_pr_rd/hw/base_trd_prj/zynq_base_trd.runs/synth_1 directory.

15. Select system_stub.ngc and click OK.

16. Mark system_stub.ngc as top-level module by checking the radio button in the Top column next to the file name.

17. Click Next.

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18. In the Add Constraints (optional) dialog, click the Add Files... button.

19. Browse to the zc702_pr_rd/hw/base_trd_prj/zynq_base_trd.srcs/sources_1/edk/xps_proj/implementation directory.

20. Select all .ncf files and click OK.

21. Click the Add Files... button again.

22. Browse to the zc702_pr_rd/hw/base_trd_prj/zynq_base_trd.srcs/constrs_1 directory.

23. Select system_stub.ucf and click OK.

24. Click the Create File... button.

25. Enter pr in the File name field and click OK.

26. Click Next.

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27. In the Default Part dialog, select Boards.

28. Select Zynq-7000 for Family, CLG484 for Package, and -1 for Speed grade.

29. Select ZYNQ-7 ZC702 Evaluation Board from the bottom view.

30. Click Next.

31. Click Finish.

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4.2 Defining a Reconfigurable Partition

Tutorial

1. From the menu bar, select Flow > Open Synthesized Deign.

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2. The Undefined Modules Found and the Critical Messages windows can be ignored. Click OK twice.
   Note: The missing netlist refers to the block that will be our reconfigurable module and hence marked as black box for now.

3. In the Netlist view of Synthesized Design, right-click the FILTER_ENGINE module and select Set Partition....

4. Click Next.

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5. In the Set Partition dialog, select is a reconfigurable Partition.

6. Click Next.

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7. Enter sobel for Reconfigurable Module Name and select Netlist already available for this Reconfigurable Module.

8. Click Next.

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9. For Top netlist file, browse to the zc702_pr_rd/hw/base_trd_prj/zynq_base_trd.srcs/sources_1/edk/xps_proj/implementation directory, select the file system_filter_sobel_wrapper.ngc and click OK.

10. Click Next.

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11. Skip the Add Constraints dialog and click Next.

12. Click Finish.

13. The Netlist view is updated showing a diamond next to the FILTER_ENGINE module and the entry sobel under Reconfigurable Modules.
    Note: The check mark inside the diamond next to sobel indicates that this module is the currently active reconfigurable module.

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4.3 Adding a Reconfigurable Module

Tutorial

1. In the Netlist view of Synthesized Design, right-click the FILTER_ENGINE module and select Add Reconfigurable Module....