Understanding clock connection in Video PHY Device Tree

Problem

Video PHY device tree can't be generated by DTG automatically. This article uses Video PHY Device Tree from HDMI Frame Buffer Design 2018.3 to explain what clocks are needed to take care in your own design.

Solution

Video PHY Device Tree v2018.3 : Documentation/devicetree/bindings/xlnx,vphy.txt

Let's have a close look at the Video PHY clock connection.

In the example below, AXI Lite clock of Video PHY is driven by &clk 71.

vid_phy_controller: vid_phy_controller@80050000 {
compatible = "xlnx,vid-phy-controller-2.2";
interrupt-parent = <&gic>;
interrupts = <0 89 4>;
reg = <0x0 0x80050000 0x0 0x10000>;
clocks = <&axi_lite_clk>, <&si570_2>;
clock-names = "axi-lite", "dru-clk";

axi_lite_clk: axi_lite_clk {
compatible = "fixed-factor-clock";
clocks = <&clk 71>;
#clock-cells = <0>;
clock-div = <1>;
clock-mult = <1>;
};

In the Framebuffer example design, AXI Lite Clock is driven from PL Clock of Zynq Ultrascale Processor. This part of clock is generated by DTG automatically, so you can find node definition in

apu\petalinux_bsp\components\plnx_workspace\device-tree\device-tree\zynqmp-clk-ccf.dtsi

fclk0: fclk0 {
status = "disabled";
compatible = "xlnx,fclk";
clocks = <&clk 71>;
};

fclk1: fclk1 {
status = "disabled";
compatible = "xlnx,fclk";
clocks = <&clk 72>;
};

fclk2: fclk2 {
status = "disabled";
compatible = "xlnx,fclk";
clocks = <&clk 73>;
};

fclk3: fclk3 {
status = "disabled";
compatible = "xlnx,fclk";
clocks = <&clk 74>;
};

In HDMI FrameBuffer Example, the AXi clock is driven from PL0 Clock , so &clk 71 is connected in axi_lite_clk node.

DRU clock is generated from on board Si570.

The Si570 clock node is defined in apu\petalinux_bsp\project-spec\meta-user\recipes-bsp\device-tree\files\zcu102\zcu102-rev1.0.dtsi

i2c@3 { /* i2c mw 74 0 8 */
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
#clock-cells = <0>;
compatible = "silabs,si570";
reg = <0x5d>;
temperature-stability = <50>;
factory-fout = <156250000>;
clock-frequency = <148500000>;
};

I2S node is defined in system_user.dtsi :

---

#include "zcu102/zcu102-rev1.0.dtsi"
#include "zcu102/pcw.dtsi"
/ {
aliases {
ethernet0 = &gem3;
i2c0 = &zynq_us_ss_0_fmch_axi_iic;
i2c1 = &i2c0;
i2c2 = &i2c1;
serial0 = &uart0;
serial1 = &uart1;
spi0 = &qspi;

};
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x7ff00000>, <0x00000008 0x00000000 0x0 0x80000000>;
};
};
#include "zcu102/system-conf.dtsi"

/* Includes */
#include "hdmi/pl.dtsi"

----

So you only need to figure out which clock is used on your own board, and use the name of node to replace si570_2 in the pl.dtsi for dru clock connection.

Xilinx Wiki

Understanding clock connection in Video PHY Device Tree

Problem

Solution

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