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Zynq UltraScale+ MPSoC VCU TRD 2019.1 - SDI Video Capture and SDI Display

Zynq UltraScale+ MPSoC VCU TRD 2019.1 - SDI Video Capture and SDI Display

Table of Contents

1 Overview

The primary goal of this Design is to demonstrate the capabilities of VCU hard block present in Zynq UltraScale+ EV devices. The TRD will serve as a platform to tune the performance parameters of VCU and arrive at optimal configurations for encoder and decoder blocks. 

This design supports the following video interfaces:

Sources:

  • SDI-Rx capture pipeline implemented in the PL.
  • File source (SD card, USB storage, SATA hard disk).
  • Stream-In from network or internet.

Sinks:

  • DP Tx display pipeline in the PS.
  • SDI-Tx display pipeline implemented in the PL.

VCU Codec:

  • Video Encode/Decode capability using VCU hard block in PL 
    • AVC/HEVC encoding.
    • Encoder/decoder parameter configuration.

Streaming Interfaces:

  • 1G Ethernet PS GEM 

Video format:

  • NV12

Audio Configuration:

  • Codec: AAC
  • Format: S24_32LE
  • Channel: 2
  • Sampling rate: 48kHz

Supported Resolution

The table below provides the supported resolution from GUI and command line app in this design.

Resolution
GUICommand Line
Single StreamSingle Stream
4kp60X
4kp30X
1080p60X

√ - Supported
NA – Not applicable
x – Not supported

The below tab