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For the overview, software tools, system requirements, design files, and board setup follow the link below:
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2 Run Flow
This section will describe the flow to run the pre-built images which each design module contains.
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Design Module # | Design | Project | Hardware Design Name |
1 | HDMI-Rx + VCU + HDMI-Tx | zcu106_trd | |
2 | PL DDR HLG SDI Audio Video Capture and Display | This Design Module is merged with Design Module #10. All functionality of this Design Module is now available with Design Module #13. | |
3 | HDMI-Rx + VCU + HDMI-Tx + Audio | zcu106_audio | |
4 | 10G HDMI Video Capture and Display | This Design Module is discontinued in 2021.2 VCU TRD release. | |
5 | PCIe Encode Decode and Transcode | This Design Module is discontinued in 2022.1 VCU TRD release. | |
6 | HDMI-Rx + VCU + HDMI-Tx + PL DDR | zcu106_HDR10_DCI4K | |
7 | Xilinx Low Latency PS DDR NV12 HDMI Audio Video Capture and Display | HDMI-Rx + VCU + HDMI-Tx + Sync IP + Audio | zcu106_llp2_audio_nv12 |
8 | Xilinx Low latency PL DDR NV16 HDMI Video Capture and Display | These two design modules are now merged as single design module #12 - Xilinx Low Latency PL DDR HDMI Video Capture and Display. | |
9 | Xilinx Low latency PL DDR NV20 HDMI Video Capture and Display | ||
10 | Xilinx Low Latency PL DDR XV20 SDI Video Capture and Display | This Design Module is merged with Design Module #2. All functionality of this Design Module is now available with Design Module #13. | |
11 | Quad Sensor MIPI CSI Video Capture and HDMI Display | This Design Module is been discontinued since 2021.1 VCU TRD release. | |
12 | HDMI-Rx + VCU + HDMI-Tx + PL DDR + Sync IP | zcu106_llp2_xv20_nv16 | |
13 | Xilinx Low Latency PL DDR HLG SDI Audio Video Capture and Display | SDI-Rx + VCU + SDI-Tx+ PL DDR + Sync IP | zcu106_picxo_llp2_sdi |
14 | HDMI-Rx + VCU + HDMI-Tx/DP | zcu106_HDMI_YUV444 | |
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This tutorial shows how to build the Linux image and boot image using the PetaLinux build tool.
PetaLinux Installation: Refer to the PetaLinux Tools Documentation UG1144 for installation. [TO DO: To be updated by 19th Oct 2022]
Kernel and DT Documentation: Refer this article for Device Tree changes and Kernel patches required for ZCU106 VCU TRD BSP.
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Design Module # | Design | Project | XSA file path |
1 | HDMI-Rx + VCU + HDMI-Tx | zcu106_trd | |
2 | PL DDR HLG SDI Audio Video Capture and Display | This Design Module is merged with Design Module #10. All functionality of this Design Module is now available with Design Module #13. | |
3 | HDMI-Rx + VCU + HDMI-Tx + Audio | zcu106_audio | |
4 | 10G HDMI Video Capture and Display | This Design Module is discontinued in 2021.2 VCU TRD release. | |
5 | PCIe Encode Decode and Transcode | This Design Module is discontinued in 2022.1 VCU TRD release. | |
6 | HDMI-Rx + VCU + HDMI-Tx + PL DDR v1 | zcu106_HDR10_DCI4K | |
HDMI-Rx + VCU + HDMI-Tx + PL DDR v2 | zcu106_HDR10_PLDDR_2_0 | ||
7 | Xilinx Low Latency PS DDR NV12 HDMI Audio Video Capture and Display | HDMI-Rx + VCU + HDMI-Tx + Sync IP + Audio | zcu106_llp2_audio_nv12 |
8 | Xilinx Low latency PL DDR NV16 HDMI Video Capture and Display | These two design modules are now merged as single design module #12 - Xilinx Low Latency PL DDR HDMI Video Capture and Display. | |
9 | Xilinx Low latency PL DDR NV20 HDMI Video Capture and Display | ||
10 | Xilinx Low Latency PL DDR XV20 SDI Video Capture and Display | This Design Module is merged with Design Module #2. All functionality of this Design Module is now available with Design Module #13. | |
11 | Quad Sensor MIPI CSI Video Capture and HDMI Display | This Design Module is been discontinued since 2021.1 VCU TRD release. | |
12 | HDMI-Rx + VCU + HDMI-Tx + PL DDR + Sync IP | zcu106_llp2_xv20_nv16 | |
13 | Xilinx Low Latency PL DDR HLG SDI Audio Video Capture and Display | SDI-Rx + VCU + SDI-Tx+ PL DDR + Sync IP | zcu106_picxo_llp2_sdi |
14 | HDMI-Rx + VCU + HDMI-Tx/DP | zcu106_HDMI_YUV444 | |
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Design Module # | Design | Project | dtsi |
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1 | HDMI-Rx + VCU + HDMI-Tx | vcu_trd.dtsi | |
2 | PL DDR HLG SDI Audio Video Capture and Display | This Design Module is merged with Design Module #10. All functionality of this Design Module is now available with Design Module #13. | |
3 | HDMI-Rx + VCU + HDMI-Tx + Audio | vcu_audio.dtsi | |
4 | 10G HDMI Video Capture and Display | This Design Module is discontinued in 2021.2 VCU TRD release. | |
5 | PCIe Encode Decode and Transcode | This Design Module is discontinued in 2022.1 VCU TRD release. | |
6 | HDMI-Rx + VCU + HDMI-Tx + PL DDR | vcu_plddr_hdr10_hdmi.dtsi | |
7 | Xilinx Low Latency PS DDR NV12 HDMI Audio Video Capture and Display | HDMI-Rx + VCU + HDMI-Tx + Sync IP + Audio | vcu_llp2_psddr_hdmi.dtsi |
8 | Xilinx Low latency PL DDR NV16 HDMI Video Capture and Display | These two design modules are now merged as single design module #12 - Xilinx Low Latency PL DDR HDMI Video Capture and Display. | |
9 | Xilinx Low latency PL DDR NV20 HDMI Video Capture and Display | ||
10 | Xilinx Low Latency PL DDR XV20 SDI Video Capture and Display | This Design Module is merged with Design Module #2. All functionality of this Design Module is now available with Design Module #13. | |
11 | Quad Sensor MIPI CSI Video Capture and HDMI Display | This Design Module is been discontinued since 2021.1 VCU TRD release. | |
12 | HDMI-Rx + VCU + HDMI-Tx + PL DDR + Sync IP | vcu_llp2_plddr_hdmi.dtsi | |
13 | Xilinx Low Latency PL DDR HLG SDI Audio Video Capture and Display | SDI-Rx + VCU + SDI-Tx+ PL DDR + Sync IP | vcu_llp2_plddr_sdi.dtsi |
14 | HDMI-Rx + VCU + HDMI-Tx/DP | vcu_yuv444.dtsi | |
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For YUV444 Capture and Display design
The YUV444 capture and display design currently requires a separate VCU firmware needed to be install to prevent performance issues. To know detailed information, please check 2022.1 2 Zynq UltraScale+ MPSoC VCU - Why do I need to install separate VCU firmware to support YUV444? [TO DO: To be updated by 19th Oct 2022]
The YUV444 pre-build images ($TRD_HOME/images/vcu_yuv444) contains VCU firmware for YUV444 in $TRD_HOME/images/vcu_yuv444/vcu/firmware directory, which will be loaded automatically on board start-up - so it is optional to perform this step, you are using YUV444 prebuild images artefacts (autostart.sh, vcu, config) along with the yuv444 petalinux build images generated by default VCU firmware.
However, if you want to include YUV444 firmware as a part of rootfs, then follow the build steps provided in above AR.
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Design Module # | Design | Project | Image Path |
1 | HDMI-Rx + VCU + HDMI-Tx | vcu_multistream_nv12 | |
2 | PL DDR HLG SDI Audio Video Capture and Display | This Design Module is merged with Design Module #10. All functionality of this Design Module is now available with Design Module #13. | |
3 | HDMI-Rx + VCU + HDMI-Tx + Audio | vcu_audio | |
4 | 10G HDMI Video Capture and Display | This Design Module is discontinued in 2021.2 VCU TRD release. | |
5 | PCIe Encode Decode and Transcode | This Design Module is discontinued in 2022.1 VCU TRD release. | |
6 | HDMI-Rx + VCU + HDMI-Tx + PL DDR v1 | vcu_plddrv1_hdr10_hdmi | |
HDMI-Rx + VCU + HDMI-Tx + PL DDR v2 | vcu_plddrv2_hdr10_hdmi | ||
7 | Xilinx Low Latency PS DDR NV12 HDMI Audio Video Capture and Display | HDMI-Rx + VCU + HDMI-Tx + Sync IP + Audio | vcu_llp2_hdmi_nv12 |
8 | Xilinx Low latency PL DDR NV16 HDMI Video Capture and Display | These two design modules are now merged as single design module #12 - Xilinx Low Latency PL DDR HDMI Video Capture and Display. | |
9 | Xilinx Low latency PL DDR NV20 HDMI Video Capture and Display | ||
10 | Xilinx Low Latency PL DDR XV20 SDI Video Capture and Display | This Design Module is merged with Design Module #2. All functionality of this Design Module is now available with Design Module #13. | |
11 | Quad Sensor MIPI CSI Video Capture and HDMI Display | This Design Module is been discontinued since 2021.1 VCU TRD release. | |
12 | HDMI-Rx + VCU + HDMI-Tx + PL DDR + Sync IP | vcu_llp2_plddr_hdmi | |
13 | Xilinx Low Latency PL DDR HLG SDI Audio Video Capture and Display | SDI-Rx + VCU + SDI-Tx+ PL DDR + Sync IP | vcu_llp2_hlg_sdi |
14 | HDMI-Rx + VCU + HDMI-Tx/DP | vcu_yuv444 | |
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Refer to the Appendix links below for the Input configuration parameters description of respective design module: [TO DO: To be updated by 19th Oct 2022]
Xilinx Low Latency PS DDR NV12 HDMI Audio Video Capture and Display - Appendix A
Xilinx Low Latency PL DDR HDMI Video Capture and Display - Appendix A
Xilinx Low Latency PL DDR HLG SDI Audio Video Capture and Display - Appendix A
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This Appendix-B section of each design module contains sample GStreamer pipelines for each relevant use-cases that individual design supports. In addition, it also covers configuration of HDMI-Rx using media-ctl utility and HDMI-Tx using modetest utility along with demonstrating HDMI-Rx/Tx link-up issues and steps to switch HDMI-Rx resolution. To get more information, refer to the Appendix links below for the respective design module: [TO DO: To be updated by 19th Oct 2022]