Zynq UltraScale+ MPSoC VCU TRD 2022.2
This page provides an overview of the 2022.2 version of the Zynq UltraScale+ MPSoC VCU TRD. This TRD is made up of several design modules. A description of the design modules and links to the individual design module pages can be found in the Design Modules below.
This page complements the TRD User Guide: UG1250
Table of Contents
1 Revision History
Change Log:
Updated all projects, IPs, and tools versions to 2022.2
2 Overview
This is the main page of the VCU TRD wiki, which has links to wiki pages corresponding to individual design modules. It also explains the complete feature list and the supported resources of all the designs. A TRD package web link is provided for the user to download. This page also gives information on the required software tools and IP licenses.
The Zynq® UltraScale+™ MPSoC Video Codec Unit (VCU) Targeted Reference Design (TRD) consists of an embedded video encoding/decoding application that runs on the Processing System (PS). The overall functionality of the TRD is partitioned between the Processing System (PS), Video Codec Unit, and Programmable Logic (PL) for optimal performance.
The primary goal of this TRD is to demonstrate the capabilities of the VCU core which is an integrated hard block present in Zynq UltraScale+ MPSoC EV devices. The TRD serves as a platform for the user to tune the performance parameters of the VCU and arrive at an optimal configuration for encoder and decoder blocks for their specific use case. The TRD uses a Vivado IP Integrator (IPI) flow for building the hardware design and Xilinx Yocto PetaLinux flow for software design. It uses Xilinx IPs and software drivers to demonstrate the capabilities of different components.
2.1 TRD Support
The TRD supports the following video interfaces.
Sources up-to 4K(3840 x 2160/4096 x 2160)-60FPS:
Test pattern generator (TPG) implemented in the PL.
HDMI-Rx capture pipeline implemented in the PL.
MIPI CSI-2 Rx capture pipeline implemented in the PL.
File source (SD card, USB storage, SATA hard disk).
Stream-In from network or internet.
SDI-Rx capture pipeline implemented in the PL.
Sinks up-to 4K(3840 x 2160/4096 x 2160)-60FPS for HDMI/SDI and 4K-30FPS for Display Port
DP Tx display pipeline in the PS.
HDMI-Tx display pipeline implemented in the PL.
SDI-Tx display pipeline implemented in the PL.
DP display pipeline implemented in the PL.
Stream-out to network or internet
VCU Codec
Video Encode/Decode capability using the VCU hard block in the PL
H.264/H.265 encoding
Encoder/decoder parameter configuration using OMX interface
Demonstrate the multi-stream capability of VCU at 4k 60 Hz throughput
Audio Codec
Opus 2 channel 48KHz
Streaming Interfaces
1G Ethernet PS GEM
Video formats
NV12 (YUV420 8-bit semi-planar format)
NV16 (YUV422 8-bit semi-planar format)
XV15 (YUV420 10-bit semi-planar format)
XV20 (YUV422 10-bit semi-planar format)
YU24 (YUV444 8-bit planar format)
X403 (YUV444 10-bit planar format)
NOTE: 8-bit or 10-bit in above video formats represents color depth.
The below figure shows the TRD block diagram. It consists of all the Design Modules. The components of each design module are highlighted in unique colors in the diagram. The remaining blocks are common to all design modules as shown.
2.2 Design Modules
The VCU TRD 2022.2 version consists of seven design-modules as described below. Individual links below will redirect to the corresponding wiki pages and build and run the flow of individual designs modules.
Design Module # | Project Name | TRD Pre-built images | Hardware design | Description |
---|---|---|---|---|
1 | vcu_multistream_nv12 | zcu106_trd | Multi-stream design supporting HDMI-Rx, TPG, MIPI, HDMI-Tx, DP along with showcasing the capabilities of the VCU | |
2 | PL DDR HLG SDI Audio Video Capture and Display | This Design Module is merged with Design Module #10. All functionality of this Design Module is now available in Design Module #13. | ||
3 | vcu_audio | zcu106_audio | Design supporting I2S and HDMI Audio with video capture of HDMI-Rx/MIPI-Rx and showcasing the capabilities of the VCU | |
4 | 10G HDMI Video Capture and Display | This Design Module is discontinued in the 2021.2 VCU TRD release. | ||
5 | PCIe Encode, Decode and Transcode | This Design Module is discontinued in the 2022.1 VCU TRD release. | ||
6 | vcu_plddrv1_hdr10_hdmi | zcu106_HDR10_DCI4K | VCU based HDMI design to showcase encoding with the PS DDR and decoding with the PL DDR. It supports the reception and insertion of HDR10 static metadata for HDMI and also the DCI4K Feature. HDR10 PLDDR_V1 corresponds to the old PLDDR part : MT40A256M16GE-075E | |
7 | Xilinx Low Latency PS DDR NV12 HDMI Audio Video Capture and Display | vcu_llp2_hdmi_nv12 | zcu106_llp2_audio_nv12 | VCU based HDMI audio video design to showcase ultra low latency support using the Sync IP, encoding and decoding with PS DDR for NV12 format |
8 | Xilinx Low latency PL DDR NV16 HDMI Video Capture and Display | |||
9 | Xilinx Low latency PL DDR NV20 HDMI Video Capture and Display | |||
10 | Xilinx Low Latency PL DDR XV20 SDI Video Capture and Display | |||
11 | Quad Sensor MIPI CSI Video Capture and HDMI Display | |||
12 | vcu_llp2_plddr_hdmi | zcu106_llp2_xv20_nv16 | VCU based HDMI design to showcase ultra low latency support using Sync IP, encoding with PS DDR and decoding with PL DDR for NV16 and XV20 format | |
13 | Xilinx Low Latency PL DDR HLG SDI Audio Video Capture and Display | vcu_llp2_hlg_sdi | zcu106_llp2_hlg_sdi | Design showcasing HLG/Non-HLG Video + 2/8 channels Audio Capture and Display through SDI interface along with the capabilities of the VCU with PL DDR supporting 4:2:2 10-bit XV20 format encoding from the PS DDR and decoding from PL DDR. It also showcases ultra low latency support using Sync IP, encoding with PS DDR and decoding with PL DDR for XV20 format. |
14 | vcu_yuv444 | zcu106_yuv444 | VCU based HDMI/DP video design to showcase YUV444 8-bit and 10-bit functionality. |