This page provides all the information related to Design Module 12 - VCU TRD Xilinx low latency (LLP2) PL DDR HDMI Video Capture and Display design.

Table of Contents

1 Overview

This module enables capture of video from an HDMI-Rx subsystem implemented in the PL. The video can be displayed through the HDMI-Tx subsystem implemented in the PL. The module can stream-out and stream-in live captured video frames through an Ethernet interface at ultra-low latencies using Sync IP. This module supports four video streams using AXI broadcaster at capture side and mixer at display side for NV16 and XV20 pixel format. In this design PL_DDR is used for decoding and PS_DDR for encoding so that DDR bandwidth would be enough to support high bandwidth VCU applications requiring simultaneous encoder and decoder operations and transcoding at 4k @60 FPS.

The VCU encoder and decoder operate in slice mode. An input frame is divided into multiple slices (8 or 16) horizontally. The encoder generates a slice_done interrupt at every end of the slice. Generated NAL unit data can be passed to a downstream element immediately without waiting for the frame_done interrupt. The VCU decoder also starts processing data as soon as one slice of data is ready in its circular buffer instead of waiting for complete frame data. The Sync IP does an AXI transaction-level tracking so that the producer and consumer can be synchronized at the granularity of AXI transactions instead of granularity at the video buffer level. Sync IP is responsible for synchronizing buffers between Capture DMA and VCU encoder as both work on same buffer.

The capture element (FB write DMA) writes video buffers in raster-scan order. SyncIP monitors the buffer level while the capture element is writing into DRAM and allows the encoder to read input buffer data if the requested data is already written by DMA, otherwise it blocks the encoder until DMA completes its writes. On the decoder side, the VCU decoder writes decoded video buffer data into DRAM in block-raster scan order and displays reads data in raster-scan order. To avoid display under-run problems, software ensures a phase difference of "~frame_period/2", so that decoder is ahead compare to display.

This design supports the following video interfaces:

Sources:

• HDMI-Rx capture pipeline implemented in the PL.

• Stream-In from network or internet.

Sinks:

• HDMI-Tx display pipeline implemented in the PL.

VCU Codec:

• Video Encode/Decode capability using VCU hard block in PL.

  • AVC/HEVC encoding

  • Encoder/decoder parameter configuration.

Video formats:

• NV16

• XV20

Supported Resolutions:

The table below provides the supported resolutions for this design.

√ - Supported
NA – Not applicable
x – Not supported

The below table gives information about the features supported in this design.

The below figure shows the Xilinx Low Latency PL DDR HDMI Video Capture and Display design hardware block diagram.

Open

The below figure shows the Xilinx Low Latency PL DDR PLDDR HDMI Video Capture and Display design software block diagram.

Open

1.1 Board Setup

Refer to the below link for Board Setup

• Zynq UltraScale+ MPSoC VCU TRD 2022.2 Board Setup

1.2 Run Flow

The TRD package is released with the source code, Vivado project, PetaLinux BSP, and SD card image that enables the user to run the demonstration. It also includes the binaries necessary to configure and boot the ZCU106 board. Prior to running the steps mentioned in this wiki page, download the TRD package and extract its contents to a directory referred to as 'TRD_HOME' - which is the home directory.

• Refer to the to Section 4.1 : Download the TRD of Zynq UltraScale+ MPSoC VCU TRD 2022.2 wiki page to download all TRD contents.

TRD package contents are placed in the following directory structure. The user needs to copy all the files from the $TRD_HOME/images/vcu_llp2_plddr_hdmi/ to FAT32 formatted SD card directory.

TRD package contents specific to VCU Xilinx Low Latency PL DDR HDMI design are placed in the following directory structure.

Configuration files(input.cfg) for various resolutions are placed in the following directory structure in /media/card.

1.2.1 GStreamer Application (vcu_gst_app)

The vcu_gst_app is a command line multi-threaded Linux application. The command line application requires an input configuration file (input.cfg) to be provided in the plain text.

Run below modetest command to set CRTC configurations for 4kp60:

Run below modetest command to set CRTC configurations for 4kp30:

Execution of the application is shown below:

Example:

4kp60 XV20/NV16 HEVC_25Mbps ultra low-latency(LLP2) display pipeline execution.

4kp60 XV20/NV16 HEVC_25Mbps ultra low-latency(LLP2) stream-out pipeline execution.

4kp60 XV20/NV16 HEVC ultra low-latency(LLP2) stream-in pipeline execution.

OR

For LLP1/LLP2 Multi-stream HEVC serial and stream-out use-cases (2-4kp30, 2-1080p60, 4-1080p60), use ENC_EXTRA_OP_BUFFERS=10 variable before vcu_gst_app command. Below is the sample pipeline:

To measure the latency of the pipeline, run the below command. The latency data is huge, so dump it to a file.

Refer to the below link for detailed run flow steps:

• Zynq UltraScale+ MPSoC VCU TRD 2022.2 - Run Flow

1.3 Build Flow

Refer to the below link for detailed build flow steps:

• Zynq UltraScale+ MPSoC VCU TRD 2022.2 - Build Flow

2 Other Information

2.1 Known Issues

• For PetaLinux related known issues please refer: PetaLinux 2022.2 - Product Update Release Notes and Known Issues

• For VCU related known issues please refer tp Answer Record 76600: LogiCORE H.264/H.265 Video Codec Unit (VCU) - Release Notes and Known Issues and Xilinx Zynq UltraScale+ MPSoC Video Codec Unit.

• To reduce performance issues with llp2 4x serial pipelines, please refer to IRQ Balancing in PG252.

2.2 Limitations

• For PetaLinux related limitations please refer: PetaLinux 2022.2 - Product Update Release Notes and Known Issues

• For VCU related limitations please refer Answer Record 76600: LogiCORE H.264/H.265 Video Codec Unit (VCU) - Release Notes and Known Issues, Xilinx Zynq UltraScale+ MPSoC Video Codec Unit and PG252.

2.3 Optimum VCU Encoder parameters for use-cases

Video streaming:

• Video streaming use-case requires very stable bitrate graph for all pictures.

• It is good to avoid periodic large Intra pictures during the encoding session

• Low-latency rate control (hardware RC) is the preferred control-rate for video streaming, it tries to maintain equal amount frame sizes for all pictures.

• Good to avoid periodic Intra frames instead use low-delay-p (IPPPPP…)

• VBR is not a preferred mode of streaming.

Performance: AVC Encoder settings:

• It is preferred to use 8 slices only for better AVC encoder performance.

• AVC standard does not support Tile mode processing which results in the processing of MB rows sequentially for entropy coding.

Quality: Low bitrate AVC encoding:

• Enable profile=high and use qp-mode=auto for low-bitrate encoding use-cases.

• The high profile enables 8x8 transform which results in better video quality at low bitrates.

3 Appendix A - Input Configuration File (input.cfg)

The example configuration files are stored at /media/card/config/ folder.