Zynq UltraScale+ MPSoC VCU TRD 2022.2 - Xilinx Low Latency PL DDR HLG SDI Audio Video Capture and Display
- Sunil Vaghela
- Sunil Vaghela
- Anamay Kane
This page provides detailed information related to Design Module 13 - Xilinx Low Latency HLG SDI Audio Video Capture and Display with PL DDR.
Table of Contents
1 Overview
The primary goal of this Design is to demonstrate the capabilities of VCU hard block present in Zynq UltraScale+ EV devices. The TRD will serve as a platform to tune the performance parameters of VCU and arrive at optimal configurations for encoder and decoder blocks. It has also added an initial support of 8-channels audio.
This module enables the capture of the Hybrid Log Gamma(HLG) video from an SDI-Rx subsystem implemented in the PL. The Hybrid Log Gamma(HLG) video can be displayed through the SDI-Tx subsystem implemented in the PL. The module can stream-out and stream-in live captured video frames through an Ethernet interface. This module supports single-stream for XV20 pixel format. In this design, PL_DDR is used for decoding and PS_DDR for encoding so that DDR bandwidth would be enough to support high bandwidth VCU applications requiring simultaneous encoder and decoder operations and transcoding at 4k@60 FPS.
The VCU encoder and decoder operate in slice mode. An input frame is divided into multiple slices (8 or 16) horizontally. The encoder generates a slice_done interrupt at every end of the slice. Generated NAL unit data can be passed to a downstream element immediately without waiting for the frame_done interrupt. The VCU decoder also starts processing data as soon as one slice of data is ready in its circular buffer instead of waiting for complete frame data. The Sync IP does an AXI transaction-level tracking so that the producer and consumer can be synchronized at the granularity of AXI transactions instead of granularity at the video buffer level. Sync IP is responsible for synchronizing buffers between Capture DMA and VCU encoder as both works on the same buffer.
The capture element (FB write DMA) writes video buffers in raster-scan order. SyncIP monitors the buffer level while the capture element is writing into DRAM and allows the encoder to read input buffer data if the requested data is already written by DMA, otherwise it blocks the encoder until DMA completes its writes. On the decoder side, the VCU decoder writes decoded video buffer data into DRAM in block-raster scan order and displays reads data in raster-scan order. To avoid display under-run problems, the software ensures a phase difference of "~frame_period/2", so that decoder is ahead compared to display.
This module supports the Encoding-Decoding and Transmission of Hybrid Log Gamma (HLG) video along with backward compatible Standard Dynamic Range (SDR) for SDI. It provides the ability to encode a wide dynamic range, while still being compatible with the existing transmission standards in the standard dynamic range (SDR) region. This HLG format encodes the HDR and SDR information in single signal enabling HDR-compatible TVs to display an enhanced image. Unlike HDR it does not have any metadata, rather it will use the Alternative transfer characteristics (ATC) and Supplemental Enhanced Information (SEI) in the Video Usability Information (VUI) to add extra encoding details.
From the VCU point of view, there are two "types" of HLG, which you can enable:
There is a HLG-SDR Backwards Compatible Mode, which uses the BT2020 value in the SPS VUI parameters instead of the HLG transfer characteristics. Then the VCU encoder will insert an 'Alternative Transfer Characteristics' (ATC) SEI with the HLG value. See the below video frame snapshot captured in the stream-eye:
Depending on version of stream-eye, you might not see SEI message correctly. However if you look at HEX viewer you will see ATC SEI in bit-stream.
0x93 - Payload Type (147 == ATC)
0x01 - Payload Size (1 byte)
0x12 - 18 (HLG EOTF value)
0x80 - payload bits ending
2. There is an HLG only mode. This directly uses the HLG value in the SPS VUI parameters. See the below frame snapshot captured in stream-eye:
This design supports the following video interfaces:
Sources:
SDI-Rx capture pipeline implemented in the PL.
File source (SD card, USB storage, SATA hard disk).
Stream-In from network or internet.
Sinks:
SDI-Tx display pipeline implemented in the PL.
VCU Codec:
Video Encode/Decode capability using VCU hard block in PL
AVC/HEVC encoding.
Encoder/decoder parameter configuration.
Streaming Interfaces:
1G Ethernet PS GEM
Video format:
XV20
Audio Configuration:
Codec: Opus
Format: S24_32LE
Channels: 2, 8
Sampling rate: 48 kHz
Supported Resolution
The table below provides the supported resolution from GUI and command-line app in this design.
Resolution | GUI | Command Line | |
Single Stream | Single Stream | Multi Stream | |
4Kp60/59.94 | X | √ | X |
4Kp30/29.97 | X | √ | X |
1080p60/59.94 | X | √ | X |
Interlaced and Fractional pipelines are not supported with LLP2.
√ - Supported
x – Not supported
The below table gives information about the features supported in this design.
Pipeline | Input Source | Output Type | ALSA Drivers | Resolution | Audio Codec Type | Audio Configuration | Video Codec | LLP2 | Deliverables |
|---|---|---|---|---|---|---|---|---|---|
Record |
SDI-Rx |
File Sink |
SDI-Rx ALSA drivers |
4K/1080p
| | 2 channel @ 48 kHz |
HEVC/AVC |
No | SDI-Rx Audio encode with soft codec and video with VCU and store it in a container format. |
| 8 channel @ 48 kHz | SDI-Rx Audio encode with soft codec and video with VCU and store it in a container format. | |||||||
|
SDI-Rx |
Stream-Out |
SDI-Rx ALSA drivers |
4K/1080p
| | 2 channel @ 48 kHz |
HEVC/AVC |
| SDI-Rx Audio encode with soft codec and video with VCU and store it in a container format. |
| 8 channel @ 48 kHz | SDI-Rx Audio encode with soft codec and video with VCU and store it in a container format. | |||||||
|
|
|
|
|
| 2 channel @ 48 kHz |
|
| Playback of the local-file/stream-in with video decoded using VCU and Audio using GStreamer soft codec. |
|
| Playback of the local-file/stream-in with video decoded using VCU and Audio using GStreamer soft codec. | |||||||
|
|
| SDI-Rx ALSA drivers and SDI-Tx ALSA drivers |
|
| 2/8 channel @ 48 kHz | HEVC/AVC |
| SDI-Rx Audio /Video pass to SDI-Tx without VCU/Audio-Codec. |
Capture → Encode → Decode → Display | | | SDI-Rx ALSA drivers and SDI-Tx ALSA drivers |
|
| 2/8 channel @ 48 kHz | HEVC/AVC |
| SDI-Rx raw audio and video with VCU encoder and decode to achieve AV sync. |
The 8-channels audio functionality is validated with Phabrix Qx 12G SDI Analyzer/Generator. also, 8-channels audio functionality is not supported with LLP2.
The below figure shows the HLG SDI Video Capture and HLG SDI Display with Audio design hardware block diagram.
The below figure shows the HLG SDI Video Capture and HLG SDI Display with Audio design software block diagram.
1.1 Board Setup
Refer to the below link for board setup
1.2 Run Flow
The TRD package is released with the source code, Vivado project, PetaLinux BSP, and SD card image that enables the user to run the demonstration. It also includes the binaries necessary to configure and boot the ZCU106 board. Prior to running the steps mentioned in this wiki page, download the TRD package and extract its contents to a directory referred to as TRD_HOME - which is the home directory.
Refer to the below link to download all TRD contents.
Refer to Section 4.1 : Download the TRD of
Zynq UltraScale+ MPSoC VCU TRD 2022.2wiki page to download all TRD contents.
TRD package contents specific to HLG SDI Video Capture and HLG SDI Display with Audio design are placed in the following directory structure. The user needs to copy all the files from the $TRD_HOME/images/vcu_llp2_hlg_sdi to FAT32 formatted SD card directory.
rdf0428-zcu106-vcu-trd-2022-2/
├── apu
│ └── vcu_petalinux_bsp
├── images
│ ├── vcu_audio
│ ├── vcu_llp2_hdmi_nv12
│ ├── vcu_llp2_hlg_sdi
│ ├── vcu_llp2_plddr_hdmi
│ ├── vcu_multistream_nv12
│ ├── vcu_plddrv1_hdr10_hdmi
│ ├── vcu_plddrv2_hdr10_hdmi
│ └── vcu_yuv444
├── pl
│ ├── constrs
│ ├── designs
│ ├── prebuild
│ ├── README.md
│ └── srcs
├── README.txt
└── zcu106_vcu_trd_sources_and_licenses.tar.gz
16 directories, 3 filesTRD package contents specific to Xilinx Low Latency PL DDR HLG SDI Audio-Video design is placed in the following directory structure.
rdf0428-zcu106-vcu-trd-2022-2
├── apu
│ └── vcu_petalinux_bsp
│ └── xilinx-vcu-zcu106-v2022.2-final.bsp
├── images
│ └── vcu_llp2_hlg_sdi
│ ├── autostart.sh
│ ├── BOOT.BIN
│ ├── bootfiles/
│ ├── boot.scr
│ ├── config/
│ ├── Image
│ ├── rootfs.cpio.gz.u-boot
│ ├── system.dtb
│ └── vcu/
├── pl
│ ├── constrs/
│ ├── designs
│ │ ├── zcu106_picxo_llp2_sdi/
│ ├── prebuild
│ │ ├── zcu106_picxo_llp2_sdi/
│ ├── README.md
│ └── srcs
│ ├── hdl/
│ └── ip/
└── README.txt
└── zcu106_vcu_trd_sources_and_licenses.tar.gzConfiguration files (input.cfg) for various Resolutions are placed in the following directory structure in /media/card.
config
├── 1080p60
│ ├── Display
│ ├── Record
│ ├── Stream-in
│ └── Stream-out
├── 4kp30
│ ├── Display
│ ├── Record
│ ├── Stream-in
│ └── Stream-out
├── 4kp60
│ ├── Display
│ ├── Record
│ ├── Stream-in
│ └── Stream-out
├── input.cfg
└── llp2
├── 1080p60
├── 4kp30
├── 4kp60
└── input.cfg1.2.1 GStreamer Application (vcu_gst_app)
The vcu_gst_app is a command-line multi-threaded Linux application. The command-line application requires an input configuration file (input.cfg) to be provided in plain text.
Execution of the application is shown below:
Example:
4kp60 HEVC_HIGH Display Pipeline execution
4kp60 HEVC_HIGH Record Pipeline execution
4kp60 HEVC_HIGH Stream-out Pipeline execution
4kp60 HEVC_HIGH Stream-in Pipeline execution
LLP2 4kp60 HEVC_HIGH Display Pipeline execution
LLP2 4kp60 HEVC_HIGH Stream-out Pipeline execution
LLP2 4kp60 HEVC_HIGH Stream-in Pipeline execution
To measure the latency of the pipeline, run the below command. The latency data is huge, so dump it to a file.
Refer to the below link for detailed run flow steps
1.3 Build Flow
Refer to the below link for build flow
2 Other Information
2.1 Known Issues
For PetaLinux related known issues please refer to: