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The Xilinx Power Estimator (XPE) is a spreadsheet-based tool that helps you to achieve this. XPE estimates the power consumption of your design at any stage during the design cycle. It accepts design information through simple design wizards, analyzes them, and provides detailed power and thermal information.
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Versal Evaluation Board - System Controller Provides generic details on the System controller on Versal.
The Jupyter notebook-based Power Advantage tool (PAT) and BEAM tool can be used to monitor and modify different parameters (clocks, voltages, power, etc.) on the evaluation boards. The BEAM tool is targeted for the Versal platforms whereas PAT is targeted for the ZynqMP platforms.
Here you can find the example using the BEAM tool to monitor the power BEAM Tool for VCK190 Evaluation Kit and Versal Adaptive SOC Power Tool part 1 - Introduction to the Power Tool. A brief description of the Versal power tool is also outlined here for a better understanding https://www.xilinx.com/about/blogs/adaptable-advantage-blog/2021/Introducing-the-Versal-Power-Tool.html
The power Advantage tool can also be used to monitor the overall system power consumption and the steps to use the same are here: Zynq UltraScale＋ MPSoC Power Advantage Tool part 1 - Introduction to the Power Advantage Tool
Source code repositories for these system controller based tools can be found here:
PetaLinux provides the system controller packages as part of its build system and you find these utilities as part of the PetaLinux here: https://github.com/Xilinx/meta-petalinux/tree/master/recipes-utils. We can use also use the sc_app command line utility of PetaLinux to monitor the power against the respective voltage rails
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RAFT is a non-system controller-based python Python toolbox which provides direct access to FPGA hardware peripherals. RAFT runs in PetaLinux and provides access to various C driver library APIs through pythonPython.
This tool uses underneath the internal implementations of Jupyter notebook based power advantage tool but it uses the regular PS Ethernet port instead of the system controller to monitor the power. We can find the relevant GitHub page that describes its usage here https://github.com/Xilinx/RAFT
Board Design Considerations for Power Management
It is a general best practice to group multiple rails into a single power supply source to optimize the overall cost of the board or control I/Os. But However, for applications requiring fine-grain power control and use cases where certain power domains can be powered-off for significant durations of time, it is essential to have independent power supply controls for LPD, FPD, and PLD.
The Board Design Considerations for Power Management cover specific PM-related design guidelines that need to be considered to enable proper runtime power management targeting the ZUZynq UltraScale+ platform
Power Management Software Solutions
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Both Zynq UltraScale+ and Versal provide ways to test its various PM features through the SW mechanism such as in the Linux Kernel. Test steps describing the PM features in the Linux including Runtime suspend/resume and the various wake-up sources outlined here: Zynq UltraScale＋ MPSoC Power Management - Linux Kernel
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We can measure transition times and respected respective power values when either the PS or PL suspends or wake up. The Typical Power States for 2020.2 (ZU+ and Versal) page describes the various ways through which the user can see/measure the suspend/wake-up time and power. These procedures are for 2020.2 and later releases.
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The section is inherited from the Power Optimization Guide for Zynq UltraScale+ MPSoC
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For PL Designs, different implementation options are presented by Vivado, including Optimization for Power. For designs targeting low power, this setting needs to be selected. It is typical to be able to save up to 30% of the PL power this way, depending on the design contents. Here is a snapshot of the selection in the “Implementation Settings” dialog.
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More detailed instructions are covered by these guides provided by Xilinx:
To enable runtime power management, there are several techniques that need to be employed in defining controls for clocks and power modes of PL IPs. These techniques are explained in detail on this page: Programmable Logic Power Management. It is typical to be able to save 40% of the PL power this way.
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