Typical Power States for 2020.2 (ZU+ and Versal)

Owned by Ravi Patel (Unlicensed)
Last updated: Apr 16, 2021
6 min read

This tutorial explains procedure to measure transition times and respected power values when either PS or PL suspends or wake up. By following below procedure, user can see/measure the suspend/wake-up time and power. These procedures are for 2020.2 and later releases.

Table of Contents

Different power states and measure transition time

Workloads on each domain

  • PLD: Petalinux prebuilt design which does not contain any specific logic

  • FPD: APU is running Linux script which controls PLD on/off and handshakes RPU for self suspend/off/resume

  • LPD: RPU is running baremetal application which controls FPD domain on/off

Prebuilt binaries for reference

For ZynqMP

For Versal

To generate binaries on your own please refer below steps for generating required images/binaries.

Generating required images/binaries

Steps to build Linux images

Create petalinux project

  • Run below commands from bash terminal to create petalinux project.

    source <petalinux-install-dir>/settings.sh petalinux-create -t project -s <xilinx zcu102/vck190 BSP location>

Build petalinux

  • Add apu_script.sh in rootfs of petalinux

    • Use below command to create and enable custom petalinux application

      petalinux-config --silentconfig petalinux-create -t apps --template install --name myapp --enable

    • Copy apu_script.sh (Use versal_apu_script.sh for versal and zynqmp_apu_script.sh for zyqmp and rename it to apu_script.sh) to myapp folder

      cp <dow_dir>/apu_script.sh <petalinux_proj_dir>/project-spec/meta-user/recipes-apps/myapp/files/

    • Update myapp.bb (located at project-spec/meta-user/recipes-apps/myapp/) as shown below

  • Enable ECC  in FSBL code (applicable only for ZynqMP):

    • Create directory <plnx-proj-root>/project-spec/meta-user/recipes-bsp/fsbl/files/ (if not present)

    • Copy patch file to <plnx-proj-root>/project-spec/meta-user/recipes-bsp/fsbl/files/ (Patch attached here: ecc_fsbl.patch)

    • Open file <plnx-proj-root>/project-spec/meta-user/recipes-bsp/fsbl/fsbl_%.bbappend (create if not present)

    • Add below lines in file:

  • Now build petalinux using below command

Steps to build RPU baremetal

  • Open Vitis and start with empty application as shown below

  • Select “create a new hardware platform“ and select petalinux prebuilt XSA file as shown below (uncheck generate boot components option in case of ZynqMP)

  • Select target processor as "psu_cortexr5_0" and give the application name (ex. rpu_app)

  • Click next and leave all options unchanged

  • Click next and select "Empty Application" from the template list

  • Click finish which will show the project window as shown below

  • Now click on "Navigate to BSP" settings and click "Modify BSP settings"

  • Now select the "xilpm" library option as shown below.

  • Select psu_cortexr5_0 and add “-DDEBUG_MODE“ in extra_compiler_flags as shown below and click ok.

  • Right click on "rpu_app" from explorer and select "import sources" option

  • Download rpu_src.tar and extract it to local folder

  • Select the source and target path as shown below and click ok

  • Right click on "rpu_app" from explorer and select "build project"

Steps to build BOOT.BIN

For ZynqMP

  • Create a new folder and copy pmufw.elf, zynqmp_fsbl.elf, bl31.elf, u-boot.elf and system.bit from petalinux generated images (present at <plnx-proj-root>/images/linux/).

  • Create RPU_0 application rpu_app.elf from Vitis as described in above section and copy rpu_app.elf into same new folder.

  • Create boot.bif file in same folder as shown below.

  • Create BOOT.BIN file using following command.

For Versal

  • Create a new folder and copy plm.elf, psmfw.elf, bl31.elf, u-boot.elf and system.dtb from petalinux generated images (present at <plnx-proj-root>/images/linux/).

  • Copy CDO files (fpd_data.cdo, lpd_data.cdo, project_1.rcdo and project_1.rnpi) present in <plnx-proj-root>/hardware to same new folder.

  • Also copy pmc_data.cdo and topology_xcvc1902.v2.cdo CDOs to same new folder.

  • Create RPU_0 application rpu_app.elf from Vitis as described in above section and copy rpu_app.elf into same new folder.

  • Copy boot.bif (use boot_vck190_es1.bif for vck190 es1, boot_vck190_prod.bif for vck190 prod, boot_vmk180_prod.bif for vmk180 prod and boot_vmk180_es1.bif for vmk180 es1) to same folder and use below command to create BOOT.BIN

Steps to run the images

Boot Linux with RPU

  • Create a boot partition in SD card and copy BOOT.BIN, boot.scr and image.ub file (present at <plnx-proj-root>/images/linux/) to boot partition.

  • Boot the board (ZCU102 in case of ZynqMP and VCK190 in case of Versal) in SD boot mode.

  • Uboot will automatically take the image.ub from SD partition and boot the linux

  • Give username and password as “root”

Measure the power and transition times

  • Use Power Advantage tool for measuring power values.

Start the demo

  • Copy apu_script.sh file from /usr/bin/ and run the script as shown below

    Note: User can open the script and edit the below parameters as per his convenient before running script
    DelayVal : Amount of delay between 2 power modes (should be between 10 to 255 seconds)
    IterationCnt: Total looping count to measure different APU power states latency (should be between 0 to 5

  • Triggering the script starts the demo and it will switch the transition from one state to next dimer state after specific amount of time (default 30 seconds)

  • User can measure the power readings using power advantage tool between intervals

  • Latency measurement values is shown as per below window

  • Once system reaches to lowest power state, it will starts reverting back to original (normal) power state as shown below

  • At the end, it will show below completion message (Full log is attached to pre-built images section)

  • User can re-trigger the apu_script.sh to re-run the demo again.

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