This page provides detailed information regarding DDR configuration and setting up IBIS simulations for the UltraScale and UltraScale+ family of FPGAs and MPSoCs.

Table of Contents

Introduction

Xilinx has determined through extensive simulation and characterization, the FPGA and DRAM configuration settings including Drive Strength, ODT, and Vref.  These values are used when the IP is generated.  This information is captured in the sections below.  The Custom IBIS models capture this information and can be used for board-level simulation.

This guide provides the following details and guidance

• Supported PL and PS DRAMs

• ODT and V_REF configuration settings for each supported DRAM interface

• IBIS Models for use in simulations

• Available resources for HyperLynx and ADS simulation tools

• HyperLynx DDRx tips

FPGA and MPSoC Supported DRAM

The UltraScale and UltraScale+ families of FPGAs and MPSoCs support several different DRAM technologies and configurations.  This chapter provides an overview of the supported DRAMs and configurations.       

Supported DRAM technologies

• FPGA, Programmable Logic (PL), DRAM IP

  • DDR4

  • DDR3/3L

• MPSoC, Processing System (PS), Configured with Processor Configuration Wizard (PCW)

  • DDR4

  • LPDDR4

  • DDR3/3L

  • LPDDR3

• MPSoC devices support both PL and PS DRAM interfaces

Supported DRAM configurations

• Table 1 outlines the supported PL DRAM configurations, PL DRAM performance, and configurations found in DS923, Maximum Physical Interface (PHY) Rate for Memory Interfaces Table.

• Table 2 outlines the supported PS DRAM performance and configurations, PS DRAM configurations found in DS925, Configuration and Security Unit Performance Table.

Table 1: Supported PL DRAM Configurations

 Table 2: Supported PS DRAM Configurations

PL DRAM IP Drive Strength, ODT, and V_REF Configuration

The PL DRAM IP has been characterized and tested to identify the optimal drive strength, ODT, and V_REF settings.  This chapter provides the values that will always be used for the PL DRAM IP UltraScale and UltraScale+ DDR3/3L and DDR4 DRAM interfaces.  The Memory Controller supports the following calibration routines.  For more details on these routines, please see PG150.

• Write Leveling

  • Write DQS to DQ Deskew

• Read Leveling

  • Per-Bit Deskew

  • Read DQS Centering

• Write Latency Calibration

  • Write DQS to CK alignment

UltraScale PL DDR4

• Table 3 provides PL DDR4 FPGA drive strength and ODT configurations

  • FPGA Slew Rate is always FAST

• Table 4 provides PL DDR4 DRAM drive strength and ODT configurations

• Table 5 provides PL DDR4 V_REF configurations

Table 3: PL DDR4 FPGA drive strength & ODT configurations

 Table 4: PL DDR4 DRAM drive strength and ODT configurations

 Table 5: PL DDR4 V_REF configurations

UltraScale PL DDR3/3L

• Table 6 provides PL DDR3/3L FPGA drive strength & ODT configuration

  • FPGA Slew Rate is always FAST

• Table 7 provides PL DDR3/3L DRAM drive strength and ODT configuration

Table 6: PL DDR3/3L FPGA drive strength & ODT configuration

 Table 7: PL DDR3/3L DRAM drive strength and ODT configuration

UltraScale+ PL DDR4

• Table 8 provides PL DDR4 FPGA drive strength & ODT configurations

  • FPGA Slew Rate is always FAST

• Table 9 provides PL DDR4 DRAM drive strength and ODT configurations

• Table 10 provides PL DDR4 V_REF configurations

Table 8: PL DDR4 FPGA drive strength & ODT configurations

Table 9: PL DDR4 DRAM drive strength and ODT configurations

Table 10: PL DDR4 V_REF configurations

UltraScale+ PL DDR3/3L

• Table 11 provides PL DDR3/3L FPGA drive strength & ODT configurations

  • FPGA Slew Rate is always FAST

• Table 12 provides PL DDR3/3L DRAM drive strength and ODT configurations

Table 11: PL DDR3/3L FPGA drive strength & ODT configurations

Table 12: PL DDR3/3L DRAM drive strength and ODT configurations