This page provides an overview of the 2020.1 version of the Zynq UltraScale+ MPSoC VCU TRD. This TRD is made up of several design modules. A description of the design modules and links to the individual design module pages can be found in the Design Modules below.
Update all projects, IPs, and tools versions to 2020.1
Added multi-stream 4x encode and 2x decode support in LLP2 HDMI designs for ultra-low-latency video pipelines
Added single-stream audio support in LLP2 HDMI NV12 design for ultra-low-latency audio and video pipelines
Added design with SDI interface and PL DDR for supporting XV20 format, interlaced feature and fractional frame rate with PICXO enabled
Added support for PCIe-based file-based transcode, encoding, and decoding with NV12, NV16, XV15 and XV20 formats
This is the main page of VCU TRD wiki, which has links to redirect wiki pages corresponding to individual design modules. It also explains the complete feature list and the supported resources of all the designs. TRD package web link is provided for the user to download. This page also gives information on required software tools, IP licenses.
The Zynq® UltraScale+™ MPSoC Video Codec Unit (VCU) Targeted Reference Design (TRD) consists of an embedded video encoding/decoding application that runs on the Processing System (PS). The overall functionality of the TRD is partitioned between the Processing System (PS), Video Codec Unit, and Programmable Logic (PL) for optimal performance.
The primary goal of this TRD is to demonstrate the capabilities of the VCU core which is an integrated hard block present in Zynq UltraScale+ MPSoC EV devices. The TRD serves as a platform for the user to tune the performance parameters of VCU and arrives at an optimal configuration for encoder and decoder blocks for their specific use case. The TRD uses Vivado IP Integrator (IPI) flow for building the hardware design and Xilinx Yocto PetaLinux flow for software design. It uses Xilinx IPs and software drivers to demonstrate the capabilities of different components.
2.1 TRD Support
The TRD supports the following video interfaces.
Sources up-to 4K(3840 x 2160/4096 x 2160)-60FPS:
Test pattern generator (TPG) implemented in the PL.
HDMI-Rx capture pipeline implemented in the PL.
MIPI CSI-2 Rx capture pipeline implemented in the PL.
File source (SD card, USB storage, SATA hard disk).
Stream-In from network or internet.
SDI-Rx capture pipeline implemented in the PL.
Sinks up-to 4K(3840 x 2160/4096 x 2160)-60FPS for HDMI/SDI and 4K-30FPS for Display Port
DP Tx display pipeline in the PS.
HDMI-Tx display pipeline implemented in the PL.
SDI-Tx display pipeline implemented in the PL.
Video Encode/Decode capability using VCU hard block in PL
Encoder/decoder parameter configuration using OMX interface
Demonstrate the multi-stream capability of VCU at 4k 60 Hz throughput
AAC 2 channel 48KHz
1G Ethernet PS GEM
10G PL Ethernet
PCIe(Peripheral Component Interconnect Express)
The below figure shows the TRD block diagram. It consists of all the Design Modules. The components of each design module are highlighted in unique colors in the diagram. The remaining blocks are common to all design modules as shown.
2.2 Design Modules
The VCU TRD 2020.1 the version consists of fourteen design-modules as described below. Individual links below will redirect to the corresponding wiki pages and build and run the flow of individual designs modules.
Design to showcase file transfer from HOST(x86) machine over PCIe interface and encode, decode or transcode it on ZCU106 board having VCU connected as PCIe endpoint and write back the encode, decoded or transcoded data to the HOST machine.
The Vivado Design Suite User Guide explains how to download and install the Vivado® Design Suite tools, which include the Vivado Integrated Design Environment (IDE), High-Level Synthesis tool, and System Generator for DSP. This guide also provides information about licensing and administering evaluation and full copies of Xilinx design tools and intellectual property (IP) products. The Vivado Design Suite can be downloaded from here.
LogiCORE IP Licensing
The following IP cores require a license to build the design.
Video Test Pattern Generator (TPG) - Included with Vivado - PG103
Video Timing Controller (VTC) - Included with Vivado - PG016
Note: Hardware Evaluation keys allow you to simulate and implement your design, run timing analysis and generate a time-limited bitstream to program a Xilinx FPGA. The core in the programmed device will function in hardware for anywhere from 2 to 8 hours, depending on the core.
The reference design has been tested successfully with the following user-supplied components.
Display Port Monitor:
Viewsonic VX2475SMHL-4K (VS16024)
3840x2160 @ 30Hz
3840x2160 @ 30Hz
1920x1080 @ 60Hz
3840x2160 @ 30Hz
3840 x 2160 @ 60Hz
1920x1080 @ 60Hz
BenQ - EW3270-T
3840 x 2160 @ 60Hz
4096 x 2160 @ 60Hz
HDMI Input Sources:
GooBang Doo ABOX 2017 player for 4kp30
NVIDIA SHIELD Pro for 4kp60
Panasonic Lumix GH5S for DCI 4kp60
Cable Matters DisplayPort Cable-E342987
Monster Advanced DisplayPort Cable-E194698
HDMI 2.0 compatible cable
3.5 Board Setup
The below section will provide the information on the ZCU106 board setup for running TRD.
Connect the Micro USB cable into the ZCU106 Board Micro USB port J83, and the other end into an open USB port on the host PC. This cable is used for UART over USB communication.
Insert the SD card with the images copied into the SD card slot J100. Please find here how to prepare the SD card for specific design.
Set the SW6 switches as shown in the below Figure. This configures the boot settings to boot from SD.
Connect 12V Power to the ZCU106 6-Pin Molex connector.
Connect one end of Display Port (DP) cable to the board’s U129 connector and the other end to DP port of the 4K monitor.
Connect one end of HDMI cable to the board’s P7 stacked HDMI connector (lower port) and another end to HDMI source in case of HDMI design.
Connect one end of HDMI cable to the board’s P7 stacked HDMI connector (upper port) and another end to HDMI monitor in case of HDMI design.
Connect one end of SDI BNC cable to HD-BNC connector (J68) on board and another end to SDI source in case of SDI design.
Connect one end of SDI BNC cable to HD-BNC connector (J10) on board and another end to SDI monitor/HDMI monitor with SDI to HDMI Converter in case of SDI design.
For a USB storage device, connect the USB hub along with the mouse. (Optional)
For SATA storage device, connect SATA data cable to SATA 3.0 port. (Optional).
For MIPI CSI-2, Insert the LI-IMX274MIPI-FMC image sensor daughter card into the FMC0 connector and set VADJ to 1.2V
The TRD package is released with the source code, Vivado project creation scripts, Petalinux BSP, and SD card image that enables the user to run the demonstration. It also includes the binaries necessary to configure and boot the ZCU106 board. Prior to running the steps mentioned in this wiki page, download the TRD package and extract its contents to a directory referred to as ‘TRD_HOME' which is the home directory.
Below figure depicts the directory structure and the hierarchy of the TRD package :
Xilinx Community Forums to ask questions or discuss technical details and issues. Please make sure to browse the existing topics first before filing a new topic. If you do file a new topic, make sure it is filed in the sub-forum that best describes your issue or question e.g. Embedded Linux for any Linux related questions. Please include "ZCU106 VCU TRD" and the release version in the topic name along with a brief summary of the issue.