This page contains specification and architecture information for the AMD Embedded Development Framework (EDF) that is applicable to specific device families, series, or portfolio.

Table of Contents

AMD Versal™ Embedded Common Platform CED and PS Specifications

AMD Versal™ AI Edge series Gen 2 Embedded Common Platform CED and PS Specifications

PS Settings

The following default PS configuration is implemented in the embedded common platform CED for Versal AI Edge series Gen 2, and is aligned with common specifications. There are also some board defined items such as fixed MIO, clocks, and enabling clock frequencies enabled by the speed grade of the target device. 

See Board Specific Settings - Board specific specifications and information

• MIO Controller - All MIO controllers (for example, I2C, SPI) associated with fixed peripherals of the platform will be enabled and configured based on the hardware board design.

• MIO I/O Configurations - All MIO default I/O controls (for example, pull-ups, slew rates) will be based on the hardware platform design. 

• Secondary Boot - Is set to "None". This reflects PLM PDI load from the secondary device, but in context of EDF secondary boot devices for boot, Linux is managed by U-Boot and not the PLM. 

• The CIPS configuration will enable the defined set of IPI to enable agreed software payloads such as XEN.  See the Board and Family specific CED specification pages for the per platform mappings.   Board specific specifications and information

NoC + AIE Path Configuration

The AIE hard block IP is to be instantiated and connected in the embedded common platform CED in order to allow for the configuration path to the AIE array as well as establishing NoC connectivity required to support the "Segmented Configuration" flow.

The overall NoC configuration of the embedded common platform CED is also maintained for users to re-generate PL designs that will be compatible with the platform boot firmware. This requires that a static NoC path configuration be maintained as part of the CED.

The CIPS configuration enables the full set of PS-NoC Master interfaces to enable all paths in the boot configuration.

Interrupts

PS-PL Interrupts

The embedded common platform CED enables one LPD interrupt (LPD INT0) and one FPD (FPD INT0) interrupt.

The following table outlines the planned application mapping and utilization of the PS-PL interrupts. TRD application PL designs will incrementally enable the PS-PL interrupts as requires. 

IPI Mappings

The embedded common platform CED enables a superset of IPI mappings to support current and future TRDs and are defined in the following table.

These do not impact the PS/PL boundary so will not be controlled relative to TRD specific PL designs. 

System Level Memory Map

The system level memory map aligns with the AMD EDF System Memory map standard Common Specifications

The implementation is dependent on the hardened IP locations within a devices global address map, which are defined in the relevant Technical Reference Manual

• Versal Adaptive SoC Technical Reference Manual (AM011)

The first table captures a high-level summary from AM011 on key sections and offsets for defining the system level DDR memory map

DDR Memory Map

The Memory Map is built based on the AMD EDF System Memory map standard Common Specifications

The following table represents the VEK385 specific map, reflecting the number of RPUs and physical memory available in the platform. 

See AMD EDF Board specific specifications and information / flows for per Evaluation board implementation

RPU configuration

In the embedded common platform CED, the RPU is set up in a "split" mode of operation. The application mapping by cluster and core is defined in the following table. 

TCM

The common CED enables TCM "Cluster All" with ECC enabled.

The TCM associated with each RPU cluster is allocated to the corresponding application SW running on that cluster.  

OCM

The embedded common platform CED enables all OCM with ECC enabled.

The OCM will be allocated to the RPU subsystem for the ISP support functionality. 

Timer Counter (AMD TTC) Assignments

The following table defines the TTC utilization with the embedded common platform CED, the CED only handles the enablement of the noted TTCs and mapping will be handled by the downstream tools.