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Board specific specifications and information

Board specific specifications and information

This page contains specification and architecture information for the AMD Embedded Development Framework (EDF) that is applicable to specific evaluation boards, including pinout, interfaces, and memory map implementation.

Table of Contents

Introduction

Evaluation board specific information can be found below, it is organized by device/device family, and then by evaluation board using the board name.

VEK385

Boot firmware and Linux disk images

Boot firmware Images - OSPI VEK385 - boot firmware + boot.pdi:

Refer to https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/3250586143/Common+Specifications#List-of-Yocto-pre-built-Machine-names-for-supported-AMD-evaluation-boards

Linux disk image - Common disk image with support for this board

Refer to https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/3250586143/Common+Specifications#EDF-Common-disk-images-containing-EDF-Linux%C2%AE-OS----Yocto-machine-definitions-and-supported-recipes

 

Boot flow - Arm System Ready compatible boot flow with UEFI

AMD EDF 25.05 (VEK385 EA) - AMD Vivado™ Design Suite 2025.1

  • u-boot uses a distro boot flow, Arm System Ready with UEFI will follow in the next release.

OSPI Memory Map - 2G Micron Device (VEK280, VEK385)

For the Micron 2b OSPI device memory device MT35XLU02G part used on VEK280, VEK385 evaluation boards.  See https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/edit-v2/3250586143#OSPI%2FQSPI-Memory-Layout---Common-Specification for more information.

This part has the same erasable and lockable sector size of 128KB, which will define the minimum footprint for each section within the OSPI memory map. The overall map is described in the table below and is aligned to the 1Gb for the "fixed" section. It can facilitate user application space for A/B images, and is pre-allocated for 114MB to accommodate the larger device targets.

Start Address

Description

Size (KB)

Start Sector

R or R/W

MTD

MultiBoot Offset

Start Address

Description

Size (KB)

Start Sector

R or R/W

MTD

MultiBoot Offset

0x0000 0000

Image Selector App

384

0

R

0

0x0000

0x0006 0000

Image Selector App - Backup

384

3

R

1

0x000C

0x000C 0000

Image Selector - Scratchpad

128

6

R

2

 

0x000E 0000

Image Recovery App

20480

7

R

3

0x001C

0x014E 0000

Image Recovery - Scratchpad

128

167

R

4

 

0x0150 0000

SystemReady-DT Update Metadata

128

168

R/W

5

 

0x0152 0000

SystemReady-DT Update Metadata (Backup)

128

169

R/W

6

 

0x0154 0000

U-Boot Variables

128

170

R/W

7

 

0x0156 0000

U-Boot Variables (Backup)

128

171

R/W

8

 

0x0158 0000

Bank "A" Image Space / Directory

116736

172

R/W

9

0x02B0

0x0878 0000

U-Boot Variables - Bank A - Design option

128

1084

R/W

10

 

0x087A 0000

U-Boot Variables - Bank A (Backup)

128

1085

R/W

11

 

0x087C 0000

Bank "B" Image Space / Directory

51200

1086

R/W

12

0x10F8

0x0F9C 0000

U-Boot Variables - Bank B - Design option

128

1998

R/W

13

 

0x0F9E 0000

U-Boot Variables - Bank B (Backup) 

128

1999

R/W

14

 

0x0FA0 0000

User Scratchpad

6016

2000

R/W

15

 

DDR Memory Map - VEK385

The VEK385 Memory Map is based on the AMD EDF System Memory map standard https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/3250586143/Common+Specifications#DDR-Memory-Map The following table represents the VEK385 specific map, reflecting the number of RPUs and physical memory available in the platform. 

Start Addr

Size (MB)

Description

Fixed/Variable

XMPU 

Start Addr

Size (MB)

Description

Fixed/Variable

XMPU 

Low DDR - 2GB

0x000 0000 0000

16

Versal PLM

Fixed

Yes - PLM FW 

0x000 0100 0000

6

TFA - Transfer list / handoffs

Fixed

TBD

0x000 0160 0000

2

TFA - Core runtime memory

Fixed

Yes - TFA FW

0x000 0180 0000

128

OP-TEE shared buffers & dynamic TAs

Fixed

Yes - Secure OS/Secure Partition

0x000 0980 0000

8

RPU Core 0-1 OpenAMP allocations (4MB / core)

x2 RPU Cores

Yes - RPU

-

32

Free memory

 

 

0x000 0C00 0000 

320 (400MB requested)

RPU+ISP reservation

x3 ISP

Yes - RPU

0x000 2000 0000

1536

Linux - Low DDR

LOW_DDR Remainder

No

High DDR

0x008 0000 0000

2048

ISP frame buffer allocation (DDRMC closest to ISPs)

Scale # ISPs

 

-

TBD

Linux - High DDR

HIGH_DDR Remainder

 

-

TBD

PL & AIE dedicated allocation(s)

 

 

Programing/flashing the OSPI (Primary boot device)

See

Programing the SD Card / UFS (Secondary Boot device)

VEK385 Basic board interfaces

The following picture shows the location of the basic board interfaces. For more information, see the Evaluation board user guide.

The basic board setup is as follows:

  1. Connect the external power supply to the "Power Input" connector (J28)

  2. Connect the USB-Type C connector (J26) labeled "FTDI USB" interface to the host PC

  3. Connect the RJ45 (J77) labeled "Versal Ethernet" to the local network

  4. Connect the RJ45 (J64) labeled "SC Ethernet" to the local network

image-20250408-063154.png

VEK385 Powering the board

To power up the board, connect the board external power supply to an outlet, plug in the external supply to the VEK385 board and turn the board on with the power switch:

image-20250408-063215.png

 

VEK385 Default DIP switch settings - boot

VEK385_Boot_Mode_Setting.png

System Controller firmware update

VEK385 UART connections - FTDI-USB

The VEK385 has four serial / UART interfaces. When the FTDI-USB cable is plugged into the VEK385 board it will create four device nodes on the host PC.

The four UART are mapped as follows,

Rev A

FDTI

System Controller

DUT (2VE3858)

FDTI

System Controller

DUT (2VE3858)

ADBUS (Device 0)

 

JTAG

BDBUS (Device 1)

PS-UART0

PS-UART1

NC

PL-UART

PS-UART0

CDBUS

PL-UART

PL-UART

DDBUS

PS-UART1

NC

Rev B

FDTI

System Controller

DUT (2VE3858)

FDTI

System Controller

DUT (2VE3858)

ADBUS (Device 0)

 

JTAG

BDBUS (Device 1)

PS-UART0

PS-UART1

NC

PL-UART

PL-UART

CDBUS

PL-UART

PS-UART0

DDBUS

PS-UART1

NC

vek385_reva_uarts.png

 

VEK385_revB_UART_BD (3).png

 

 

SC UART

Versal PS-UART1 is used by the primary user software (U-Boot and Linux). This can be directly accessed by the host PC via the FTDI UART. 

Versal PS-UART0 is used by default for auxiliary software (PLM, ASU, RPU) and on Rev A boards is routed to the System Controller for remote UART functionality. In Rev B of the VEK385, PS-UART0 is directly accessible via the FTDI-USB interface. It is a known limitation in this configuration that PLM power-on messages will not be accessible in this VEK385 Rev A configuration. Users can work around this by issuing a Versal POR_B and capturing logs at System Controller. 

VEK385 Base Vivado Design for BSPs and PS specifications

This specification inherits from the common and device specific specifications, but also has evaluation board specific items. See also the following:

 

The Versal Gen 2 AI Edge Series Gen 2 Embedded Common Platform CED from AMD Vivado™ Design Suite 2025.1 is the base Vivado design used for EDF BSPs.

it is the recommended starting point for Vivado designs to maintain compatibility with the pre-built OSPI boot images, and EDF pre-built disk images.

VEK385 PL Board I/O

The Base CED PL design includes an AXI-GPIO controllers that shall be make use of the "GPIO" physical interfaces for customer test. These are summarized in the following table. They are split across unique controllers to align with mapping to Vivado Board File signal groups and to minimize customer confusion on bitwise definitions.

Controller

Description

Location

PL IP Direction

Controller

Description

Location

PL IP Direction

PL_AXI_GPIO_0

GPIO_LED[3:0]

Bank 705 & 706

Output

PL_AXI_GPIO_1

GPIO_PB[1:0]

Bank 705 & 706

Input

PL_AXI_GPIO_2

GPIO_DIP[3:0]

Bank 705 & 706

Input

VEK385 MMI Configuration

The MMI configuration for VEK385 is aligned with the VEK385 hardware design. This includes the following configurations:

  • Base Configuration

    • PCIe 10GbE HSDP GT = PCIe0 x2 10GbE

    • USB DisplayPort GT = DP X2 + USB

    • USB Configuration

      • USB3.2 = Enabled

      • USB2.0 = Enabled (will be automatic with 3.2 enable)

  • 10GbE Configuration

    • Data Rate = 10G

    • MDIO = Not enabled / None

    • External FIFO = Not enabled

    • External TSU Interface = Not enabled

    • PTP Interface = Not enabled

  • DPDC Configuration

    • Operating Mode = DC Functional

    • Presentation Mode = Non Live

    • Video Interface Mode = Native

    • DP Hot Plug Detect = PMC MIO 48

  • MMI PCIE Controller 0

    • Link

      • Port Type = Root Port of PCIe Root Port Complex

      • Link Speed = 32 GT/s

      • Mode = TBD

      • PERST = None (Will be handed by SW)

    • PF Basic, PF BARs, SRIOV - N/A as in root port mode

VEK385 MMI clocks:

  • Video Clocks - Derived off a common MBUFGCE

    • MMI 2x Clk = 600MHz

    • MMI 1x Clk = 300MHz

  • Audio Clock

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