This page contains specification and architecture information for the AMD Embedded Development Framework (EDF) that is applicable to specific device families, series, or portfolio.

1 AMD Versal™ Embedded Common Platform CED and PS Specifications
- 1.1 AMD Versal™ AI Edge series Gen 2 Embedded Common Platform CED and PS Specifications
  - 1.1.1 PS Settings
    - 1.1.1.1 NoC + AIE Path Configuration
  - 1.1.2 Interrupts
    - 1.1.2.1 PS-PL Interrupts
    - 1.1.2.2 IPI Mappings
    - 1.1.2.3 System Level Memory Map
    - 1.1.2.4 DDR Memory Map
  - 1.1.3 RPU configuration
  - 1.1.4 TCM
  - 1.1.5 OCM
  - 1.1.6 Timer Counter (AMD TTC) Assignments
  - 1.1.7 PS-PL Clocks
    - 1.1.7.1 Linux Kernel and RootFS Configuration
- 1.2 AMD Versal™ AI Core and AI Edge series Embedded Common Platform CED and PS Specifications
  - 1.2.1 PS Specifications:
    - 1.2.1.1 PS Peripheral mappings in the CED
  - 1.2.2 Interrupts
    - 1.2.2.1 PS-PL Interrupts
    - 1.2.2.2 IPI Mappings
    - 1.2.2.3 DDR Memory Map
    - 1.2.2.4 System Level Memory Map
2 Related Links
3 Child Pages
4 Trademarks

AMD Versal™ Embedded Common Platform CED and PS Specifications

AMD Versal™ AI Edge series Gen 2 Embedded Common Platform CED and PS Specifications

This specification inherits from the common specification, but also has evaluation board specific items. See also the following:

PS Settings

The following default PS configuration is implemented in the embedded common platform CED for Versal AI Edge series Gen 2, and is aligned with common specifications. There are also some board defined items such as fixed MIO, clocks, and enabling clock frequencies enabled by the speed grade of the target device.

See Board Specific Settings - Board specific specifications and information | VEK385

MIO Controller - All MIO controllers (for example, I2C, SPI) associated with fixed peripherals of the platform will be enabled and configured based on the hardware board design.
MIO I/O Configurations - All MIO default I/O controls (for example, pull-ups, slew rates) will be based on the hardware platform design.
Secondary Boot - Is set to "None". This reflects PLM PDI load from the secondary device, but in context of EDF secondary boot devices for boot, Linux is managed by U-Boot and not the PLM.
The CIPS configuration will enable the defined set of IPI to enable agreed software payloads such as XEN. See the Board and Family specific CED specification pages for the per platform mappings. Board specific specifications and information

NoC + AIE Path Configuration

The AIE hard block IP is to be instantiated and connected in the embedded common platform CED in order to allow for the configuration path to the AIE array as well as establishing NoC connectivity required to support the "Segmented Configuration" flow.

The overall NoC configuration of the embedded common platform CED is also maintained for users to re-generate PL designs that will be compatible with the platform boot firmware. This requires that a static NoC path configuration be maintained as part of the CED.

The CIPS configuration enables the full set of PS-NoC Master interfaces to enable all paths in the boot configuration.

Interrupts

PS-PL Interrupts

The embedded common platform CED enables one LPD interrupt (LPD INT0) and one FPD (FPD INT0) interrupt.

The following table outlines the planned application mapping and utilization of the PS-PL interrupts. TRD application PL designs will incrementally enable the PS-PL interrupts as requires.

Note: These allocations are not fixed/static in the silicon design but a "template" to minimize differences across AMD owned reference designs. Mappings are shared for TRDs and SLT Designs.

Domain	IRQ	Enabled	Allocation	AMD Example Designs - Linux	AMD Example Designs - BM

Domain	IRQ	Enabled	Allocation	AMD Example Designs - Linux	AMD Example Designs - BM
LPD	0	Yes	ISP0 Functions	visp_ss_0/tile0_isp_isr_irq	visp_ss_0/tile0_isp_isr_irq
LPD	1	Yes	ISP0 Functions	visp_ss_0/tile0_isp_xmpu_interrupt	visp_ss_0/tile0_isp_xmpu_interrupt
LPD	2	Yes	ISP0 Functions	visp_ss_0/tile0_isp0_fusa_irq	visp_ss_0/tile0_isp0_fusa_irq
LPD	3	Yes	ISP0 Functions	visp_ss_0/tile0_isp0_isp_irq	visp_ss_0/tile0_isp0_isp_irq
LPD	4	Yes	ISP0 Functions	visp_ss_0/tile0_isp1_fusa_irq	visp_ss_0/tile0_isp1_fusa_irq
LPD	5	Yes	ISP0 Functions	visp_ss_0/tile0_isp1_isp_irq	visp_ss_0/tile0_isp1_isp_irq
LPD	6	Yes	ISP1 Functions	visp_ss_0/tile1_isp_isr_irq
LPD	7	Yes	ISP1 Functions	visp_ss_0/tile1_isp_xmpu_interrupt
LPD	8	Yes	ISP1 Functions	visp_ss_0/tile1_isp0_fusa_irq
LPD	9	Yes	ISP1 Functions	visp_ss_0/tile1_isp0_isp_irq
LPD	10	Yes	ISP1 Functions	visp_ss_0/tile1_isp1_fusa_irq
LPD	11	Yes	ISP1 Functions	visp_ss_0/tile1_isp1_isp_irq
LPD	12	Yes	ISP2 Functions	visp_ss_0/tile2_isp_isr_irq	vmix_frmbuf_rd_ss/v_frmbuf_rd_0/interrupt
LPD	13	Yes	ISP2 Functions	visp_ss_0/tile2_isp_xmpu_interrupt	vmix_frmbuf_rd_ss/v_frmbuf_rd_1/interrupt
LPD	14	Yes	ISP2 Functions	visp_ss_0/tile2_isp0_fusa_irq
LPD	15	Yes	ISP2 Functions	visp_ss_0/tile2_isp0_isp_irq	frmbuf_wr_ss/v_frmbuf_wr_0/interrupt
LPD	16	Yes	ISP2 Functions	visp_ss_0/tile2_isp1_fusa_irq	frmbuf_wr_ss/v_frmbuf_wr_1/interrupt
LPD	17	Yes	ISP2 Functions	visp_ss_0/tile2_isp1_isp_irq	frmbuf_wr_ss/v_frmbuf_wr_2/interrupt
LPD	18	Yes	PL Apps	frmbuf_rd_ss	frmbuf_wr_ss/v_frmbuf_wr_3/interrupt
LPD	19	Yes	PL Apps	frmbuf_wr_ss
LPD	20	Yes	PL Apps	vmix_ss	vmix_ss
LPD	21	Yes	PL Apps	axi_timer_hdmi	axi_timer_hdmi
LPD	22	Yes	PL Apps	v_hdmi_txss1	v_hdmi_txss1
LPD	23	Yes	PL Apps	hdmiphy_ss_0/hdmi_gt_controller	hdmiphy_ss_0/hdmi_gt_controller
FPD	0	Yes	PL Apps	pl_axi_intc (for MIPI interrupts)
FPD	1	Yes	PL Apps	VCU - IRQ_ERROR
FPD	2	Yes	PL Apps	VCU _ Decoder
FPD	3	Yes	PL Apps	VCU_Encoder
FPD	4	Yes	PL Apps		mipi_rx (0XB100_0000)
FPD	5	Yes	PL Apps		mipi_rx (0XB106_0000)
FPD	6	Yes	PL Apps	axi_iic_hdmi	axi_iic_hdmi
FPD	7	Yes	PL Apps	hdmi_rxss	hdmi_rxss

IPI Mappings

The embedded common platform CED enables a superset of IPI mappings to support current and future TRDs and are defined in the following table.

These do not impact the PS/PL boundary so will not be controlled relative to TRD specific PL designs.

IPI	Enabled	Master	Description

IPI	Enabled	Master	Description
IPI PMC	Yes	PMC	Platform management functions
IPI PMC No BUF	Yes	PMC	Platform management functions
IPI ASU	Yes	ASU	Security management functions
IPI 0	Yes	A78_0	APU SW to map functions
IPI 1	Yes	R52_0	RPU SW/RTOS function (TBD)
IPI 2	Yes	A78_0	APU SW to map functions
IPI 3	Yes	A78_0	APU SW to map functions
IPI 4	Yes	A78_0	APU SW to map functions
IPI 5	Yes	A78_0	APU SW to map functions
IPI 6	Yes	A78_0	APU SW to map functions
IPI NOBUF 1	Yes	A78_0	OpenAMP example app (APU)
IPI NOBUF 2	Yes	R52_0	OpenAMP example app (RPU)
IPI NOBUF 3	Yes	R52_6	ISP support functions
IPI NOBUF 4	Yes	R52_7	ISP support functions
IPI NOBUF 5	Yes	R52_8	ISP support functions
IPI NOBUF 6	Yes	R52_9	ISP support functions

System Level Memory Map

The system level memory map aligns with the AMD EDF System Memory map standard Common Specifications | System Level Memory Map

The implementation is dependent on the hardened IP locations within a devices global address map, which are defined in the relevant Technical Reference Manual

Versal Adaptive SoC Technical Reference Manual (AM011)

The first table captures a high-level summary from AM011 on key sections and offsets for defining the system level DDR memory map

Start Addr	Description

Start Addr	Description
0x000 0000 0000	DDRMC0 - Region 0
0x000 8000 0000	Versal internal memory maps
0x008 0000 0000	DDRMC0 - Region 1
0x0C0 0000 0000	DDRMC0 - Region 2
0x100 0000 0000	DDRMC0 - Region 3
0x200 0000 0000	AIE Memory Map
0x201 0000 0000	PL Memory Map
0x400 0000 0000	PS-PL Memory Map
0x500 0000 0000

Device specific specifications and information

Table of Contents