This page provides tips and examples of power management solutions for Zynq UltraScale+ MPSoC , RFSoC and the Versal Adaptive SoC Core, Prime, and Premium devices.

Table of Contents

Software Solutions

• Linux Power Management

• Typical Power States 2020.2

• Power Optimization Guide for Zynq UltraScale+ MPSoC

• ZCU102 SW Design Examples

• Software Tips

Versal Adaptive SoC Power tool

The Versal Power Tool lets the user monitor the power of their design during development. This is available through the AMD Evaluation Board BEAM Tool, but can also be run from the Python3 command prompt. Part 4 contains code snippets to extend the measurement system to 1 ms intervals (like scope), to support a 48 hour measurement with logging, customized UI, etc.

• Part 1 – Introduction to the Power Tool

• Part 2 – Installing the Pre-Built Power Tool

• Part 3 – Running the Pre-Built Power Tool

• Part 4 – Developing with the Power Tool

Zynq UltraScale+ MPSoC Power Advantage Tool

• Part 1 – Introduction to the Power Advantage Tool

• Part 2 – Installing the Pre-Built Power Advantage Tool

• Part 3 – Running the Pre-Built Power Advantage Tool

• Part 4 – Building and Running the SD Image

• Part 5 – Building and Running the PL Design From Sources

• Part 6 – Building and Running the R5 Design From Sources

• Part 7 – Building and Running the MSP430 Design from Sources

• Part 8 – Building and Running the Qt PC GUI Design from Sources

• Part 9 – Building and Installing the Gimp Artwork from Sources

• Part 10 – Building and Running the Linux Design From Sources

Power Management Videos

• PS: Power Management Features

• PS: Power Advantage Tool

• PS: Enabling PS Power Management

• PS: PS Power Islands

• PS: Frequency Scaling

• PS: Power Domain Switching

• PS: Driver-Based Power Management

• PL: PL Power Management Overview

• PL: PL Clock Control Types

• PL: PL Clock Control Implementation

• PL: FPGA Only Power Management Architectures

• PL: External FPGA Power Management

• PL: PL PM Design For Early Implementation and Reuse

• Adv: Schematic Design For Power Management

• Adv: DDR Power Optimization

• Adv: FSBL Power Management

• Adv: Debug Nodes

• Adv: Debug Registers

• Adv: Interconnect Clock and Standby

• Adv: Peripheral Clocks

• Adv: Saving PLLs

• Adv: Hard IP Power Management

• Adv: Applying all to VCU TRD

Product Documents

• UG1304 Versal Adaptive SoC System Software Developers Guide

• UG1200 Embedded Energy Management Interface

• AM011 Versal Adaptive SoC Technical Reference Manual

• UG1304 Versal Software Developer Guide

• UG1137 Zynq UltraScale+ MPSoC Software Developer Guide

• UG1200 Embedded Energy Management Interface