This page provides an overview of the 2021.2 version of the Zynq UltraScale+ MPSoC VCU TRD.  This TRD is made up of several design modules.  A description of the design modules and links to the individual design module pages can be found in the Design Modules below.

This page complements the TRD User Guide: UG1250

Table of Contents

1 Revision History

Change Log:

• Updated all projects, IPs, and tools versions to 2021.2

• Deprecated 10G HDMI Video Capture and Display design

• Merged LLP2 PL DDR HDMI NV16 and LLP2 PL DDR HDMI XV20 in single design (Design Module #12)

• Added HDR10 Pass-through use-case support

2 Overview

This is the main page of VCU TRD wiki, which has links to redirect wiki pages corresponding to individual design modules. It also explains the complete feature list and the supported resources of all the designs. TRD package web link is provided for the user to download. This page also gives information on required software tools, IP licenses.

The Zynq® UltraScale+™ MPSoC Video Codec Unit (VCU) Targeted Reference Design (TRD) consists of an embedded video encoding/decoding application that runs on the Processing System (PS). The overall functionality of the TRD is partitioned between the Processing System (PS), Video Codec Unit, and Programmable Logic (PL) for optimal performance. 

The primary goal of this TRD is to demonstrate the capabilities of the VCU core which is an integrated hard block present in Zynq UltraScale+ MPSoC EV devices. The TRD serves as a platform for the user to tune the performance parameters of VCU and arrives at an optimal configuration for encoder and decoder blocks for their specific use case. The TRD uses Vivado IP Integrator (IPI) flow for building the hardware design and Xilinx Yocto PetaLinux flow for software design. It uses Xilinx IPs and software drivers to demonstrate the capabilities of different components.

2.1 TRD Support

The TRD supports the following video interfaces.

Sources up-to 4K(3840 x 2160/4096 x 2160)-60FPS:

• Test pattern generator (TPG) implemented in the PL.

• HDMI-Rx capture pipeline implemented in the PL.

• MIPI CSI-2 Rx capture pipeline implemented in the PL.

• File source (SD card, USB storage, SATA hard disk).

• Stream-In from network or internet.

• SDI-Rx capture pipeline implemented in the PL.

Sinks up-to 4K(3840 x 2160/4096 x 2160)-60FPS for HDMI/SDI and 4K-30FPS for Display Port

• DP Tx display pipeline in the PS.

• HDMI-Tx display pipeline implemented in the PL.

• SDI-Tx display pipeline implemented in the PL.

VCU Codec

• Video Encode/Decode capability using VCU hard block in PL 

  • H.264/H.265 encoding

  • Encoder/decoder parameter configuration using OMX interface

  • Demonstrate the multi-stream capability of VCU at 4k 60 Hz throughput

Audio Codec

• Opus 2 channel 48KHz 

Streaming Interfaces

• 1G Ethernet PS GEM

Serial Communication

• PCIe(Peripheral Component Interconnect Express)

Video format

• NV12

• NV16

• XV15

• XV20

The below figure shows the TRD block diagram. It consists of all the Design Modules. The components of each design module are highlighted in unique colors in the diagram. The remaining blocks are common to all design modules as shown.