This page provides an overview of the 2019.2 version of the Zynq UltraScale+ MPSoC VCU TRD. This TRD is made up of of several design modules. A description of the design modules and links to the individual design module pages can be found in the Design Modules section below.
Table of Contents
1 Revision History
This wiki page complements the2019.2 a version of the MPSoC VCU TRD.
Update all projects, IPs, and tools versions to 2019.2
Added single-channel stream-based SCD and HDMI video support to the multistream audio design.
Added multistream and DCI 4k resolution support to the PL DDR HDMI design.
Added new LLP2 designs with HDMI interface supporting NV12, NV16 and XV20 formats for ultra-low-latency support.
Added LLP2 design with the SDI interface supporting XV20 format for ultra-low-latency support.
Added a design with SDI interface and plddr for supporting XV20 format and interlaced feature.
Added support for PCIe-based file encoding and decoding.
This is the main page of VCU TRD wiki, which has links to redirect wiki pages corresponding to individual design modules. It also explains the complete feature list and the supported resources of all the designs. TRD package web link is provided for the user to download. This page also gives information on required software tools, IP licenses.
The Zynq® UltraScale+™ MPSoC Video Codec Unit (VCU) Targeted Reference Design (TRD) consists of an embedded video encoding/decoding application that runs on the Processing System (PS). The overall functionality of the TRD is partitioned between the Processing System (PS), Video Codec Unit, and Programmable Logic (PL) for optimal performance.
The primary goal of this TRD is to demonstrate the capabilities ofthe VCU core which is an integrated hard block present in Zynq UltraScale+ MPSoC EV devices. The TRD serves as a platform for the user to tune the performance parameters of VCU and arrives at an optimal configuration for encoder and decoder blocks for their specific use case. The TRD uses Vivado IP Integrator (IPI) flow for building the hardware design and Xilinx Yocto PetaLinux flow for software design. It uses Xilinx IPs and software drivers to demonstrate the capabilities of different components.
2.1 TRD Support
The TRD supports the following video interfaces.
Sources up-to 4K(3840 x 2160/4096 x 2160)-60FPS:
Test pattern generator (TPG) implemented in the PL.
HDMI-Rx capture pipeline implemented in the PL.
MIPI CSI-2 Rx capture pipeline implemented in the PL.
File source (SD card, USB storage, SATA hard disk).
Stream-In from network or internet.
SDI-Rx capture pipeline implemented in the PL.
Sinks up-to 4K(3840 x 2160/4096 x 2160)-60FPS for HDMI/SDI and 4K-30FPS for Display Port
DP Tx display pipeline in the PS.
HDMI-Tx display pipeline implemented in the PL.
SDI-Tx display pipeline implemented in the PL.
Video Encode/Decode capability using VCU hard block in PL
Encoder/decoder parameter configuration using OMX interface
Demonstrate the multi-stream capability of VCU at 4k 60 Hz throughput
AAC 2 channel 48KHz
1G Ethernet PS GEM
10G PL Ethernet
PCIe(Peripheral Component Interconnect Express)
The below figure shows the TRD block diagram.It consists of all the Design Modules. The components of each design module are highlighted in unique colors in the diagram. The remaining blocks are common to all design modules as shown.
2.2 Design Modules
The VCU TRD 2019.2 the version consists of fourteen design-modules as described below. Individual links below will redirect to the corresponding wiki pages and build and run the flow of individual designs modules.
Design showcasing Audio Video Capture and Display through SDI interface along with the capabilities of VCU along with PLDDR supporting 4:2:2 10 bit XV20 format encoding from PS DDR and decoding from PLDDR
Design to showcase file transfer from HOST(x86) machine over PCIe interface and encode, decode or transcode it on ZCU106 Board having VCU connected as PCIe endpoint and write back the encode, decoded or transcoded data to the HOST machine.
The Vivado Design Suite User Guide explains how to download and install the Vivado® Design Suite tools, which include the Vivado Integrated Design Environment (IDE), High-Level Synthesis tool, and System Generator for DSP. This guide also provides information about licensing and administering evaluation and full copies of Xilinx design tools and intellectual property (IP) products. The Vivado Design Suite can be downloaded from here.
LogiCORE IP Licensing
The following IP cores require a license to build the design.
Video Test Pattern Generator (TPG) - Included with Vivado
Video Timing Controller (VTC) - Included with Vivado
Copy the TRD images into the SD card and insert the SD card on the board.
The below images will show how to connect interfaces on the ZCU106 board.
The above figure shows all the zcu106 board connections
The above figure shows all the zcu106 board connector slots
Determine which COM to use to access the USB serial port on the ZCU106 board. Make sure that the ZCU106 board is powered on and a micro USB cable is connected between the ZCU106 board and host PC. This ensures that the USB-to-serial bridge is enumerated by the PC host.
Open your computer's Control Panel by clicking on Start > Control Panel.
Note that the Start button is typically located in the lower-left corner of the screen. Occasionally, it is in the upper left corner.
Click Device Manager to open the Device Manager window. Note: You may be asked to confirm opening the Device Manager. If so, click YES.
Expand Ports (COM & LPT).
Locate the Silicon Labs Quad CP210x USB to UART Bridge: Interface 0 (COM#).
4. Note down the COM Port number for further steps. 5. Close the Device Manager by clicking the red X in the upper right corner of the window.
Launch any Terminal application like Tera term to view the serial messages
Launch Tera Term and open the COM the port that is associated with Silicon Labs Quad CP210x USB to UART Bridge: Interface 0 of the USB-to-serial bridge.
Set the COM port to 115200 Baud rate, 8, none, 1 –Set COM port.
Power ON the board which has an SD card. Switch ON SW1 to power the ZCU106 board.
It boots Linux on board and It takes about a minute for Linux to boot.
4 Design Files
4.1 Download the TRD
The TRD supports Rev C, D, E, F and Rev 1.0 ZCU106 evaluation boards with Production silicon.
The TRD package is released with the source code, Vivado project creation scripts, Petalinux BSP, and SD card image that enables the user to run the demonstration. It also includes the binaries necessary to configure and boot the ZCU106 board. Prior to running the steps mentioned in this wiki page, download the TRD package and extract its contents to a directory referred to as ‘TRD_HOME' which is the home directory.
Below figure depicts the directory structure and the hierarchy of the TRD package :
The top-level directory structure is described below:
apu: It contains VCU Petalinux BSP.
vcu_petalinux_bsp: It contains VCU TRD 2019.2 Petalinux BSP
pcie_host_x86: It contains the HOST drivers and application for PCIe transcode use case.
documentation: It contains test reports for all supported 2019.2 VCU TRD designs.
images: It contains pre-built binaries i.e BOOT.BIN and image.ub, config files and necessary scripts for all supported 2019.2 designs.
pl: This directory consists of subdirectories like - pre-built XSA's, Project creation scripts, Design constraints and the HDL source files required to create hardware project
5 Other Information
5.1 Known Issues
Refer to the individual wiki page links for known issues and limitations of that particular design.
To obtain technical support for this reference design, go to the:
Xilinx Community Forums to ask questions or discuss technical details and issues. Please make sure to browse the existing topics first before filing a new topic. If you do file a new topic, make sure it is filed in the sub-forum that best describes your issue or question e.g. Embedded Linux for any Linux related questions. Please include "ZCU106 VCU TRD" and the release version in the topic name along with a brief summary of the issue.