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Zynq UltraScale+ MPSoC VCU TRD 2019.2 - PCIe

Zynq UltraScale+ MPSoC VCU TRD 2019.2 - PCIe

Zynq UltraScale+ MPSoC VCU TRD 2019.2 - PCIe


Table of Contents

1 Overview

The primary goal of this Design is to demonstrate the file-based VCU transcode, encode and decode capabilities over PCIe present in Zynq UltraScale+ EV devices.


This design supports the following interfaces:

VCU Codec:

  • Video Encode/Decode capability using VCU hard block in PL 
    • AVC/HEVC encoding.
    • Encoder/decoder parameter configuration.

Communication Interface:

  • PCIe

Video format:

  • NV12
  • NV16 (Only for transcode and decode use case)

Supported Resolution:

The table below provides the supported resolution from the command line app only in this design.

Resolution
Command Line
Single Stream
4kp60
4kp30
1080p60