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Design Module # | Project Name | TRD Pre-built images | Description |
|---|---|---|---|
1 | vcu_multistream_nv12 | Multi-stream design supporting HDMI-Rx, TPG, MIPI, HDMI-Tx, DP along with showcasing capabilities of VCU. | |
2 | vcu_sdi_xv20 | Design showcasing Audio Video Capture and Display through SDI interface along with the capabilities of VCU with PL DDR supporting 4:2:2 10 bit XV20 format encoding from PS DDR and decoding from PL DDR | |
3 | vcu_audio | Design supporting I2S and HDMI Audio with video capture of HDMI-Rx/MIPI-Rx and showcasing capabilities of VCU | |
4 | vcu_10g | Design showcasing Video stream over 10G Ethernet along with the capabilities of VCU | |
5 | vcu_pcie | Design to showcase file transfer from HOST(x86) machine over PCIe interface and encode, decode or transcode it on ZCU106 board having VCU connected as PCIe endpoint and write back the encode, decoded or transcoded data to the HOST machine. | |
6 | vcu_hdmirx | Design showcasing Video Capture through HDMI interface along with the capabilities of VCU | |
7 | vcu_hdmitx | Design showcasing Video Display through HDMI interface along with the capabilities of VCU | |
8 | vcu_sdirx | Design showcasing Video Capture only through SDI interface along with the capabilities of VCU | |
9 | vcu_sditx | Design showcasing SDI transmit capabilities along with the capabilities of the VCU | |
10 | vcu_hdmi_multistream_xv20 | VCU based HDMI design to showcase encoding with PS DDR and decoding with PL DDR | |
11 | Xilinx Low Latency PS DDR NV12 HDMI Audio Video Capture and Display | vcu_llp2_hdmi_nv12 | VCU based HDMI audio video design to showcase ultra low latency support using Sync IP, encoding and decoding with PS DDR for NV12 format |
12 | Xilinx Low Latency PL DDR NV16 HDMI Video Capture and Display | vcu_llp2_hdmi_nv16 | VCU based HDMI design to showcase ultra low latency support using Sync IP, encoding with PS DDR and decoding with PL DDR for NV16 format |
13 | Xilinx Low Latency PL DDR XV20 HDMI Video Capture and Display | vcu_llp2_hdmi_xv20 | VCU based HDMI design to showcase ultra low latency support using Sync IP, encoding with PS DDR and decoding with PL DDR for XV20 format |
14 | Xilinx Low Latency PL DDR XV20 SDI Video Capture and Display | vcu_llp2_sdi_xv20 | VCU based SDI design to showcase ultra low latency support using Sync IP, encoding with PS DDR and decoding with PL DDR for XV20 format |
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rdf0428-zcu106-vcu-trd-2020.-1 ├── apu │ └── vcu_petalinux_bsp ├── images │ ├── vcu_10g │ ├── vcu_audio │ ├── vcu_hdmi_multistream_xv20 │ ├── vcu_hdmi_rx │ ├── vcu_hdmi_tx │ ├── vcu_llp2_hdmi_nv12 │ ├── vcu_llp2_hdmi_nv16 │ ├── vcu_llp2_hdmi_xv20 │ ├── vcu_llp2_sdi_xv20 │ ├── vcu_multistream_nv12 │ ├── vcu_pcie │ ├── vcu_sdirx │ ├── vcu_sditx │ └── vcu_sdi_xv20 ├── pcie_host_package │ ├── COPYING │ ├── include │ ├── libxdma │ ├── LICENSE │ ├── readme.txt │ ├── RELEASE │ ├── tests │ ├── tools │ └── xdma ├── pl │ ├── constrs │ ├── designs │ ├── prebuild │ ├── README.md │ └── srcs └── README.txt 28 directories, 6 files |
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