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This page provides an overview of the 2019.2 version of the Zynq UltraScale+ MPSoC VCU TRD.  This TRD is made up of of several design modules.  A description of the design modules and links to the individual design module pages can be found in the Design Modules section below. 


Table of Contents
excludeTable of Contents

1 Revision History

This wiki page complements the 2019.2 a version of the MPSoC VCU TRD.

Change Log:

  • Update all projects, IPs, and tools versions to 2019.2
  • Added single-channel stream-based SCD and HDMI video support to the multistream audio design.
  • Added multistream and DCI 4k resolution support to the PL DDR HDMI design.
  • Added new LLP2 designs with HDMI interface supporting NV12, NV16 and XV20 formats for ultra-low-latency support.
  • Added LLP2 design with the SDI interface supporting XV20 format for ultra-low-latency support.
  • Added a design with SDI interface and plddr for supporting XV20 format and interlaced feature.
  • Added support for PCIe-based file encoding and decoding.


This is the main page of VCU TRD wiki, which has links to redirect wiki pages corresponding to individual design modules. It also explains the complete feature list and the supported resources of all the designs. TRD package web link is provided for the user to download. This page also gives information on required software tools, IP licenses.

The Zynq® UltraScale+™ MPSoC Video Codec Unit (VCU) Targeted Reference Design (TRD) consists of an embedded video encoding/decoding application that runs on the Processing System (PS). The overall functionality of the TRD is partitioned between the Processing System (PS), Video Codec Unit, and Programmable Logic (PL) for optimal performance. 

The primary goal of this TRD is to demonstrate the capabilities of the VCU core which is an integrated hard block present in Zynq UltraScale+ MPSoC EV devices. The TRD serves as a platform for the user to tune the performance parameters of VCU and arrives at an optimal configuration for encoder and decoder blocks for their specific use case. The TRD uses Vivado IP Integrator (IPI) flow for building the hardware design and Xilinx Yocto PetaLinux flow for software design. It uses Xilinx IPs and software drivers to demonstrate the capabilities of different components.

2.1 TRD Support

The TRD supports the following video interfaces.


Serial Communication

  • PCIe(Peripheral Component Interconnect Express)

Video format:

  • NV12
  • NV16
  • XV15
  • XV20

The below figure shows the TRD block diagram. It consists of all the Design Modules. The components of each design module are highlighted in unique colors in the diagram. The remaining blocks are common to all design modules as shown.

design modules
design modules
2.2 Design Modules


  1. Connect the Micro USB cable into the ZCU106 Board Micro USB port J83, and the other end into an open USB port on the host PC. This cable is used for UART over USB communication.
  2. Insert the SD card with the images copied into the SD card slot J100. Please find here how to prepare the SD card for specific design.
  3. Set the SW6 switches as shown in the below Figure. This configures the boot settings to boot from SD.
  4. Connect 12V Power to the ZCU106 6-Pin Molex connector.
  5. Connect one end of Display Port (DP) cable to the board’s U129 connector and the other end to DP port of the 4K monitor.
  6. Connect one end of HDMI cable to the board’s P7 stacked HDMI connector (lower port) and another end to HDMI source in case of HDMI design.
  7. Connect one end of HDMI cable to the board’s P7 stacked HDMI connector (upper port) and another end to HDMI monitor in case of HDMI design.
  8. Connect one end of SDI BNC cable to HD-BNC connector (J68) on board and another end to SDI source in case of SDI design.
  9. Connect one end of SDI BNC cable to HD-BNC connector (J10) on board and another end to SDI monitor/HDMI monitor with SDI to HDMI Converter in case of SDI design.
  10. For a USB storage device, connect the USB hub along with the mouse. (Optional)
  11. For SATA storage device, connect SATA data cable to SATA 3.0 port. (Optional).
  12. For MIPI CSI-2, Insert the LI-IMX274MIPI-FMC image sensor daughter card into the FMC0 connector and set VADJ to 1.2V (See FMC VADJ Voltage Settings).

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  13. Set up a terminal session between a PC COM port and the serial port on the evaluation board (See the  Determine which COM to use to access the USB serial port on the ZCU106 board for more details).
  14. Copy the TRD images into the SD card and insert the SD card on the board.
  15. The below images will show how to connect interfaces on the ZCU106 board.