Title: Zynq UltraScale+ MPSoC VCU TRD 2019.2  
Owner: Saket Kumar Bafna
Creator: Saket Kumar Bafna Sept 18, 2019
Last Changed by: Mohammed Rafi Shaik Jun 02, 2020
Tiny Link: (useful for email) https://xilinx-wiki.atlassian.net/wiki/x/I4CJCg
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    Page: Technical Articles
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Children (15)
    Page: Zynq UltraScale+ MPSoC VCU TRD 2019.2 - Run and Build Flow
    Page: Zynq UltraScale＋ MPSoC VCU TRD 2019.2 - VCU TRD : Multi Stream
    Page: Zynq UltraScale＋ MPSoC VCU TRD 2019.2 - SDI Video Capture and SDI Display with PLDDR
    Page: Zynq UltraScale＋ MPSoC VCU TRD 2019.2 - Multi stream Audio-Video Design
    Page: Zynq UltraScale＋ MPSoC VCU TRD 2019.2 - 10G HDMI Video Capture and HDMI Display
    Page: Zynq UltraScale＋ MPSoC VCU TRD 2019.2 - PCIe
    Page: Zynq UltraScale＋ MPSoC VCU TRD 2019.2 - HDMI Video Capture
    Page: Zynq UltraScale＋ MPSoC VCU TRD 2019.2 - HDMI Video Display
    Page: Zynq UltraScale＋ MPSoC VCU TRD 2019.2 - SDI Video Capture
    Page: Zynq UltraScale＋ MPSoC VCU TRD 2019.2 - SDI Video Display
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Time Editor  
Jun 02, 2020 08:21 Mohammed Rafi Shaik View Changes
Jun 01, 2020 21:02 Mohammed Rafi Shaik View Changes
Jun 01, 2020 20:54 Mohammed Rafi Shaik View Changes
Apr 21, 2020 17:12 Terry O'Neal View Changes
intro, TOC
Jan 16, 2020 20:21 Chris Arndt  
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Xilinx Wiki (8)     Page: Zynq UltraScale＋MPSoC VCU TRD 2019.2 - Xilinx Low Latency PS DDR NV12 HDMI Video Capture and Display
    Page: Zynq UltraScale＋MPSoC VCU TRD 2019.2 - Xilinx Low Latency PL DDR XV20 HDMI Video Capture and Display
    Page: Zynq UltraScale＋MPSoC VCU TRD 2019.2 - Xilinx Low Latency PL DDR NV16 HDMI Video Capture and Display
    Page: Zynq UltraScale+ MPSoC VCU TRD 2019.2
    Page: Zynq UltraScale＋ MPSoC VCU TRD 2019.2 - HDMI Video Capture
    Page: Zynq UltraScale＋ MPSoC VCU TRD 2019.2 - HDMI Video Display
    Page: Zynq UltraScale＋MPSoC VCU TRD 2019.2 - Xilinx Low Latency PL DDR XV20 SDI Video Capture and Display
    Page: Zynq UltraScale＋ MPSoC VCU TRD 2019.2 - PL DDR HDMI Video Capture and Display