- zynqmp-clk-ccf.dtsi has static clock node configuration, if user wants to change any of the clock information update those in system-user.dtsi.
- Multi concat Interrupt blocks wont be supported by the DTG.
- DTG doesn't support IP that are packaged in a subsystem(multiple BD's)
- Interrupt port width more than one wont be supported.
- When multicore is enabled for the MAC IPs(if the MAC IPs are more than 1) then there is issue with the label in DTG and it fails. But there wont be an issue if the MAC IP is one and multicore is enabled.
- DTG wont support for generation of private peripheral interrupts(PPI).
- DTG supports the video pipeline generation based on the internal TRD designs as mentioned in the wiki https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/25329832/Zynq+UltraScale+MPSoC+VCU+TRD+2018.3
- DTG doesn't support custom IP, For Multimedia use case If there are any custom IPs connected between the video pipeline IPs DTG wont support those, user may need to add the input and output ports.
- For broadcaster IP the output can connect to multiple output ports and DTG cant know which output port is a valid for the correct pipeline.
- If there are multiple similar video pipelines in the design user need to add the input and output port information in the nodes. The below wiki gives some info about how to add the input and output ports.
- DTG doesn't support non memory-mapped IP's.
- DTG limitation for multimedia IPs
New Features for
- Added mrmac IP initial support.
- Added DPU IP support
- Replaced the hardcoded values with the macros for reset and power.
- Added dma channels for axi_mcdma IP support in DTG.
- Generate the memory node for each axi_noc IP for Versal
- Added dfx support in DTG
- generating the aie clock node for versal designs if they have aie ip.
- For aie node you can find the detailed doc in below
List of drivers supported in the DTG and their bindings in Linux tree
- can, canfd
- axi_ethernet, axi_10g_ethernet,xxv_ethernet
cd linux-xlnx/scripts/dtc make ARCH=arm <devicetree name>.dtb dtx_diff system1.dtb system2.dtb
Advanced DTG Topics
generate dfx supported dtsi files (only for versal)
This section explains how to generate the dtsi files that supports dfx flow.
1.clone the device-tree
https://github.com/Xilinx/device-tree-xlnx.git -b xlnx_rel_v2022.1
i.xsct % setws <workspace dir name>
ii.xsct % repo -set <above cloned device-tree-xlnx path>
iii.xsct % platform create -name dev -hw <static xsa path> -rm-hw <rp-rm xsa path> -proc <proc> -os device_tree
iv.xsct % bsp config dt_overlay true
v.xsct % platform generate
you will find static and partial dtsi files in the <workspace dir>/dev/psv_cortexa72_0/device_tree_domain/bsp/
convert them into dtbo files using the compiling steps.
How to enable DT OVERLAY from DTG
This section only focuses on DTG aspects of devicetree overlays. For more comprehensive information on using overlays refer to the applicable FPGA Manager driver page. Links to the applicable page can be found under Linux Drivers.
- 2016.4 DTG Release Notes
- 2018.3 Release Notes for Open Source Components (see DTG section)
- 2022.1 Release Notes for Open Source Components (see DTG section)
- Build FSBL
- Build Device Tree Compiler (DTC)
- Build PMU Firmware
- Build Arm Trusted Firmware (ATF)
- Build U-Boot
- Build and Modify a Root File System
- (You are here) Build Device Tree Blob
- Build Linux Kernel
- Prepare Boot Image
- Prepare Boot Medium
- Setup a Serial Console
- Additional Information: Build Qt and Qwt Libraries