Table of Contents

1 Revision History

This wiki page complements the 2018.3 version of the MPSoC VCU TRD.

Change Log:

• Update all projects, IPs, and tools versions to 2018.3
• HDMI Audio integrated into TRD
• Multistream support – Maximum 8 streams (7 HDMI, 1 MIPI)
• PS GEM for stream out and stream in (capture->encode->stream-out  <->  stream-in-> Decode→display)
• 10G Ethernet stream out and stream in (capture->encode->stream-out  <->  stream-in-> Decode→display)
• Two new MINI reference designs added (HDMI TX and SDI TX ) 
• HDMI Video captures and Display with SDSoC.

2 Overview

This is the main page of VCU TRD wiki, which has links to redirect wiki pages corresponding to individual design modules. It also explains the complete feature list and the supported resources of all the designs. TRD package weblink is provided for the user to download. This page also gives information on required software tools, IP licenses.

The Zynq® UltraScale+™ MPSoC Video Codec Unit (VCU) Targeted Reference Design (TRD) consists of an embedded video encoding/decoding application that runs on the Processing System (PS). The overall functionality of the TRD is partitioned between the Processing System (PS), Video Codec Unit, and Programmable Logic (PL) for optimal performance. 

The primary goal of this TRD is to demonstrate the capabilities of the VCU core which is an integrated hard block present in Zynq UltraScale+ MPSoC EV devices. The TRD serves as a platform for the user to tune the performance parameters of VCU and arrives at an optimal configuration for encoder and decoder blocks for their specific use case. The TRD uses Vivado IP Integrator (IPI) flow for building the hardware design and Xilinx Yocto PetaLinux flow for software design. It uses Xilinx IPs and software drivers to demonstrate the capabilities of different components

The TRD supports the following video interfaces:
Sources  (up-to 4K-60FPS):

• Test pattern generator (TPG) implemented in the PL.
• HDMI-Rx capture pipeline implemented in the PL.
• MIPI CSI-2 Rx capture pipeline implemented in the PL.
• File source (SD card, USB storage, SATA hard disk).
• Stream-In from network or internet.
• SDI-Rx capture pipeline implemented in the PL.

Sinks (up-to 4K-60FPS for HDMI and 4K-30FPS for Display Port):

• DP Tx display pipeline in the PS.
• HDMI-Tx display pipeline implemented in the PL.
• SDI-Tx display pipeline implemented in the PL.

VCU Codec:

• Video Encode/Decode capability using VCU hard block in PL 
  • H.264/H.265 encoding
  • Encoder/decoder parameter configuration using OMX interface
  • Demonstrate multi-stream capability of VCU at 4k 60 Hz throughput

Audio Codec :

• AAC 2 channel 48KHz 

Streaming Interfaces:

• 1G Ethernet PS GEM 
• 10G PL Ethernet

The below figure shows the TRD block diagram. It consists of all the Design Modules. The components of each design module are highlighted in unique colors in the diagram. The remaining blocks are common to all design modules as shown.

The VCU TRD 2018.3 version consists of nine design-modules as described below. Individual links below will redirect to the corresponding wiki pages and build and run flow of individual designs modules. 

VCU TRD User guide has more details about the list of features, software architecture, and hardware architecture of individual designs. Here is the link for the user guide :

• Zynq UltraScale+ MPSoC VCU TRD user guide, UG1250

3 Software Tools and System Requirements

3.2 Software Tools