CEDStore: AXI DMA on VCK190
Tutorial: Versal Embedded Design, section on Versal ACAP CIPS and NoC (DDR) IP Core Configuration
CEDStore: Simulating with the CIPS Verification IP
This user brings together the ACAP hardware, board design and software and needs system level debug tools to diagnose and resolve performance and power issues.
Tutorial: Versal Embedded Design, section on Debugging Using the Vitis Software Platform
Tutorial: Versal JTAG Boot Tutorial
This post shows how to route a configuration complete signal from the PMC to the PL.
This user cares about system software interactions with the NoC and DDR MC. This typically occurs during error reporting and handling.
This user tends not to care about the NoC and DDR MC.