This page provides an overview of the 2022.1 version of the Zynq UltraScale+ MPSoC VCU TRD. This TRD is made up of several design modules. A description of the design modules and links to the individual design module pages can be found in the Design Modules below.
Updated all projects, IPs, and tools versions to 2022.1
Deprecated PCIe HDMI Video Capture and Display design
Merged LLP2 PL DDR SDI and PL DDR HLG SDI in single design (Design Module #13)
Added support for YUV444 8-bit/10-bit design (Design Module #14)
This is the main page of the VCU TRD wiki, which has links to wiki pages corresponding to individual design modules. It also explains the complete feature list and the supported resources of all the designs. A TRD package web link is provided for the user to download. This page also gives information on the required software tools and IP licenses.
The Zynq® UltraScale+™ MPSoC Video Codec Unit (VCU) Targeted Reference Design (TRD) consists of an embedded video encoding/decoding application that runs on the Processing System (PS). The overall functionality of the TRD is partitioned between the Processing System (PS), Video Codec Unit, and Programmable Logic (PL) for optimal performance.
The primary goal of this TRD is to demonstrate the capabilities of the VCU core which is an integrated hard block present in Zynq UltraScale+ MPSoC EV devices. The TRD serves as a platform for the user to tune the performance parameters of the VCU and arrive at an optimal configuration for encoder and decoder blocks for their specific use case. The TRD uses a Vivado IP Integrator (IPI) flow for building the hardware design and Xilinx Yocto PetaLinux flow for software design. It uses Xilinx IPs and software drivers to demonstrate the capabilities of different components.
2.1 TRD Support
The TRD supports the following video interfaces.
Sources up-to 4K(3840 x 2160/4096 x 2160)-60FPS:
Test pattern generator (TPG) implemented in the PL.
HDMI-Rx capture pipeline implemented in the PL.
MIPI CSI-2 Rx capture pipeline implemented in the PL.
File source (SD card, USB storage, SATA hard disk).
Stream-In from network or internet.
SDI-Rx capture pipeline implemented in the PL.
Sinks up-to 4K(3840 x 2160/4096 x 2160)-60FPS for HDMI/SDI and 4K-30FPS for Display Port
DP Tx display pipeline in the PS.
HDMI-Tx display pipeline implemented in the PL.
SDI-Tx display pipeline implemented in the PL.
DP display pipeline implemented in the PL.
Stream-out to network or internet
Video Encode/Decode capability using the VCU hard block in the PL
Encoder/decoder parameter configuration using OMX interface
Demonstrate the multi-stream capability of VCU at 4k 60 Hz throughput
Opus 2 channel 48KHz
1G Ethernet PS GEM
NV12 (YUV420 8-bit semi-planar format)
NV16 (YUV422 8-bit semi-planar format)
XV15 (YUV420 10-bit semi-planar format)
XV20 (YUV422 10-bit semi-planar format)
YU24 (YUV444 8-bit planar format)
X403 (YUV444 10-bit planar format) NOTE: 8-bit or 10-bit in above video formats represents color depth.
The below figure shows the TRD block diagram. It consists of all the Design Modules. The components of each design module are highlighted in unique colors in the diagram. The remaining blocks are common to all design modules as shown.
2.2 Design Modules
The VCU TRD 2022.1 version consists of eight design-modules as described below. Individual links below will redirect to the corresponding wiki pages and build and run the flow of individual designs modules.
Design showcasing HLG/Non-HLG Video + 2/8 channels Audio Capture and Display through SDI interface along with the capabilities of the VCU with PL DDR supporting 4:2:2 10-bit XV20 format encoding from the PS DDR and decoding from PL DDR. It also showcases ultra low latency support using Sync IP, encoding with PS DDR and decoding with PL DDR for XV20 format.
The Vivado Design Suite User Guideexplains how to download and install the Vivado® Design Suite tools, which include the Vivado Integrated Design Environment (IDE), High-Level Synthesis tool, and System Generator for DSP. This guide also provides information about licensing and administering evaluation and full copies of Xilinx design tools and intellectual property (IP) products. The Vivado Design Suite can be downloaded from here.
LogiCORE IP Licensing
The following IP cores require a license to build the design.
Video Test Pattern Generator (TPG) - Included with Vivado - PG103
Video Timing Controller (VTC) - Included with Vivado - PG016
Note: Hardware Evaluation keys allow you to simulate and implement your design, run timing analysis and generate a time-limited bitstream to program a Xilinx FPGA. The core in the programmed device will function in hardware for anywhere from 2 to 8 hours, depending on the core.
The reference design has been tested successfully with the following user-supplied components.
Display Port Monitor:
Viewsonic VX2475SMHL-4K (VS16024)
3840 x 2160 @ 30Hz
LG 27MU67-B / LG 24UD58
3840 x 2160 @ 30Hz
1920 x 1080 @ 60Hz
3840 x 2160 @ 30Hz
3840 x 2160 @ 60Hz
3840 x 2160 @ 60Hz
1920 x 1080 @ 60Hz
BenQ - EW3270-T
3840 x 2160 @ 60Hz
ColorEdge CG319X - DCI-4K monitor
4096 x 2160 @ 60Hz
One-plus TV (model: 55Q1) - HDR10 monitor
3840 x 2160 @ 60Hz
HDMI Input Sources:
GooBang Doo ABOX 2017 player for 4kp30
NVIDIA SHIELD Pro for 4kp60
Panasonic Lumix GH5S for DCI 4kp60
MI-BOX for YUV444 10-bit
Cable Matters DisplayPort Cable-E342987
Monster Advanced DisplayPort Cable-E194698
HDMI 2.0 compatible cable
3.5 Board Setup
The below section will provide the information on the ZCU106 board setup for running TRD.
Connect the Micro USB cable into the ZCU106 Board Micro USB port J83, and the other end into an open USB port on the host PC. This cable is used for UART over USB communication.
Insert the SD card with the images copied into the SD card slot J100. Please find here how to prepare the SD card for specific design.
Set the SW6 switches as shown in the below Figure. This configures the boot settings to boot from SD.
Connect 12V Power to the ZCU106 6-Pin Molex connector.
Connect one end of the Display Port (DP) cable to the board’s U129 connector and the other end to the DP port of the 4K monitor.
Connect one end of the HDMI cable to the board’s P7 stacked HDMI connector (lower port) and another end to the HDMI source in case of HDMI design.
Connect one end of the HDMI cable to the board’s P7 stacked HDMI connector (upper port) and another end to the HDMI monitor in case of HDMI design.
Important Note: It is highly recommended to disconnect the DP or HDMI cable whenever it is not in use. Using both simultaneously might lead to unexpected behavior.
Connect one end of the SDI BNC cable to the HD-BNC connector (J68) on the board and another end to the SDI source in case of an SDI design.
Connect one end of the SDI BNC cable to the HD-BNC connector (J10) on the board and another end to the SDI monitor/HDMI monitor with the SDI to HDMI Converter in case of an SDI design.
For a USB storage device, connect the USB hub along with the mouse. (Optional)
For SATA storage device, connect the SATA data cable to the SATA 3.0 port. (Optional)
For MIPI CSI-2, Insert the LI-IMX274MIPI-FMC image sensor daughter card into the FMC0 connector and set VADJ to 1.2V
Copy the TRD images into the SD card and insert the SD card on the board.
The below images will show how to connect interfaces on the ZCU106 board.
Determine which COM to use to access the USB serial port on the ZCU106 board
Make sure that the ZCU106 board is powered on and that a micro USB cable is connected between the ZCU106 board and host PC. This ensures that the USB-to-serial bridge is enumerated by the PC host.
Open your computer's Control Panel by clicking on Start > Control Panel.
Note that the Start button is typically located in the lower-left corner of the screen. Occasionally, it is in the upper left corner.
Click Device Manager to open the Device Manager window. Note: You might be asked to confirm opening the Device Manager. If so, click YES.
Expand Ports (COM & LPT).
Locate the Silicon Labs Quad CP210x USB to UART Bridge: Interface 0 (COM#).
4. Note down the COM Port number for further steps. 5. Close the Device Manager by clicking the red X in the upper right corner of the window.
Launch any Terminal application like Tera term to view the serial messages
Launch Tera Term and open the COM the port that is associated with Silicon Labs Quad CP210x USB to UART Bridge: Interface 0 of the USB-to-serial bridge.
Set the COM port to 115200 Baud rate, 8 bit data, none parity, 1 stop bit.
Power ON the board which has an SD card. Switch ON SW1 to power the ZCU106 board.
It boots Linux on board and it takes about a minute for Linux to boot.
4 Design Files
4.1 Download the TRD
The TRD supports Rev C, D, E, F and Rev 1.0 ZCU106 evaluation boards with Production silicon.
Download the TRD 2022.1 release package from here.
This rdf package has zcu106_vcu_trd_sources_and_licenses.tar.gz file, which contains the sources and licensing information for all PetaLinux recipes used to generated VCU TRD images.
4.2 TRD Directory Structure and Package Contents
The TRD package is released with the source code, Vivado project creation scripts, PetaLinux BSP, and SD card image that enables the user to run the demonstration. It also includes the binaries necessary to configure and boot the ZCU106 board. Prior to running the steps mentioned in this wiki page, download the TRD package and extract its contents to a directory referred to as TRD_HOME - which is the home directory.
The below figure depicts the directory structure and the hierarchy of the TRD package:
The top-level directory structure is described below:
apu: It contains the VCU PetaLinux BSP.
vcu_petalinux_bsp: It contains VCU TRD 2022.1 PetaLinux BSP.
zcu106_vcu_trd_sources_and_licenses.tar.gz: Thisfile contains sources and licensing information of all PetaLinux recipes used to generate VCU TRD images.
images: It contains pre-built binaries i.e BOOT.BIN, boot.scr, system.dtb, Image and rootfs.cpio.gz.u-boot, config files and necessary scripts for all supported 2022.1 designs. It also contains bootfiles (i.e. bl31.elf, bootgen.bif, pmufw.elf, system.bit, u-boot.elf, zynqmp_fsbl.elf) - which are helpful to generate BOOT.BIN.
pl: This directory consists of sub-directories like - pre-built XSA's, Project creation scripts, Design constraints and the HDL source files required to create hardware project
5 Other Information
5.1 Known Issues
Refer to the individual wiki page links for known issues and limitations of that particular design.
To obtain technical support for this reference design, go to the:
Xilinx Community Forums to ask questions or discuss technical details and issues. Please make sure to browse the existing topics first before filing a new topic. If you do file a new topic, make sure it is filed in the sub-forum that best describes your issue or question e.g. Embedded Linux for any Linux related questions. Please include "ZCU106 VCU TRD" and the release version in the topic name along with a brief summary of the issue.