Zynq UltraScale+ MPSoC VCU TRD 2022.1 - VCU TRD Multi Stream Video Capture and Display
This page provides all of the information related to Design Module 1 - VCU TRD Multi Stream Video capture and display design.
Table of Contents
1 Overview
The primary goal of this design is to demonstrate the capabilities of the VCU hard block present in Zynq UltraScale+ EV devices. The TRD will serve as a platform to tune the performance parameters of the VCU and arrive at optimal configurations for encoder and decoder blocks. This module supports seven HDMI video streams using AXI4 Stream Broadcaster IP at the capture side and eight video streams using mixer at the display side for NV12 pixel format.
This design supports the following video interfaces:
Sources:
Test pattern generator (TPG) implemented in the PL
HDMI-Rx capture pipeline implemented in the PL
MIPI CSI-2 Rx capture pipeline implemented in the PL
File source (SD card, USB storage, SATA hard disk)
Stream-In from network or internet
Sinks:
DP-Tx display pipeline in the PS
HDMI-Tx display pipeline implemented in the PL
VCU Codec:
Video Encode/Decode capability using VCU hard block in PL
AVC/HEVC encoding
Encoder/decoder parameter configuration.
Demonstrate the multi-stream capability of VCU at 4K 60 Hz throughput
Streaming Interfaces:
1G Ethernet PS GEM
Video format:
NV12
This design demonstrates the multi-stream capability of VCU at 4K 60 Hz throughput.
Supports 2-4Kp30 multi-stream feature with any 2 of HDMI-Rx, TPG, and MIPI as the input source and HDMI-Tx as the display pipeline.
Supports 4-1080p60 multi-stream feature with 3 HDMI-Rx and 1 MIPI as the input source and HDMI-Tx as the display pipeline.
Supports 8-1080p30 multi-stream feature with 7 HDMI-Rx and 1 MIPI as the input source and HDMI-Tx as the display pipeline.
Other features:
This design supports 8 channel memory-based Scene Change Detection (SCD) IP. SCD can be enabled or disabled through configuration.
Supported Resolution:
The table below provides the supported resolution from the GUI and command-line app in this design.
Resolution | GUI | Command Line | |
Single Stream | Single Stream | Multi-stream | |
4Kp60 | X | √ | NA |
4Kp30 | √ | √ | √ (Max 2) |
1080p60 | √ | √ | √ (Max 4) |
1080p30 | X | √ | √ (Max 8) |
√- Supported
x - Not supported
NA - Not applicable
The below table gives information about the features supported in this design.
Pipeline | Input Source | Output Type | Resolution | VCU Codec |
---|---|---|---|---|
Pass-through/RAW Pipeline: | HDMI-Rx / MIPI / TPG | HDMI-Tx / DP | 4K / 1080p | None |
Single Stream: | HDMI-Rx / MIPI / TPG | HDMI-Tx / DP | 4K / 1080p | HEVC / AVC |
Multi-Stream (2 input sources): | HDMI-Rx / MIPI / TPG | HDMI-Tx | 4Kp30 | HEVC / AVC |
Multi-Stream(4 input sources): | HDMI-Rx / MIPI / TPG | HDMI-Tx | 1080p60 | HEVC / AVC |
Multi-Stream(8 input sources): | 7-HDMI-Rx + 1 MIPI | HDMI-Tx | 1080p30 | HEVC / AVC |
Single Stream: Record/Stream-Out pipeline | HDMI-Rx / MIPI / TPG | File Sink / Stream-Out | 4K / 1080p | HEVC / AVC |
Multi-Stream(2 or 4 i/p sources): Record / Stream-Out pipeline | HDMI-Rx / MIPI / TPG | File Sink / Stream-Out | 2-4Kp30 / 4-1080p60 | HEVC / AVC |
Multi-Stream(8 input sources): Record / Stream-Out pipeline | 7-HDMI-Rx + 1 MIPI | File Sink / Stream-Out | 8-1080p30 | HEVC / AVC |
File Playback / Streaming pipeline | File Source / Stream-In | HDMI-Tx / DP | 4K / 1080p | HEVC / AVC |
DP supports a max resolution of 4Kp30.
TPG will not support 1080p30 resolution mode.
The below figure shows the VCU TRD Multi Stream Video capture and display design hardware block diagram.
The below figure shows the VCU TRD Multi Stream Video capture and display design software block diagram.
1.1 Board Setup
Refer to the below link for Board Setup