version 2.0
# subsystem_3
pm_add_subsystem 0x1c000003
# subsystem_4
pm_add_subsystem 0x1c000004
# subsystem_3 dev_ocm_bank_0
pm_add_requirement 0x1c000003 0x18314007 0x8304 0xfffff
# subsystem_3 dev_ocm_bank_1
pm_add_requirement 0x1c000003 0x18314008 0x8304 0xfffff
# subsystem_3 dev_ocm_bank_2
pm_add_requirement 0x1c000003 0x18314009 0x8304 0xfffff
# subsystem_3 dev_ocm_bank_3
pm_add_requirement 0x1c000003 0x1831400a 0x8304 0xfffff
# subsystem_3 dev_ams_root
pm_add_requirement 0x1c000003 0x18224055 0x4 0xfffff
# subsystem_3 dev_acpu_0
pm_add_requirement 0x1c000003 0x1810c003 0x8104 0xfffff
# subsystem_3 dev_acpu_1
pm_add_requirement 0x1c000003 0x1810c004 0x8104 0xfffff
# subsystem_3 dev_gem_0
pm_add_requirement 0x1c000003 0x18224019 0x8704 0x38
# subsystem_3 dev_gem_1
pm_add_requirement 0x1c000003 0x1822401a 0x8704 0x38
# subsystem_3 dev_sdio_0
pm_add_requirement 0x1c000003 0x1822402e 0x8104 0x38
# subsystem_3 dev_sdio_1
pm_add_requirement 0x1c000003 0x1822402f 0x8104 0xfffff
# subsystem_3 dev_can_fd_0
pm_add_requirement 0x1c000003 0x1822401f 0x4 0xfffff
# subsystem_3 dev_i2c_0
pm_add_requirement 0x1c000003 0x1822401d 0x4 0xfffff
# subsystem_3 dev_spi_0
pm_add_requirement 0x1c000003 0x1822401b 0x4 0xfffff
# subsystem_3 dev_can_fd_1
pm_add_requirement 0x1c000003 0x18224020 0x4 0xfffff
# subsystem_3 dev_i2c_1
pm_add_requirement 0x1c000003 0x1822401e 0x4 0xfffff
# subsystem_3 dev_spi_1
pm_add_requirement 0x1c000003 0x1822401c 0x4 0xfffff
# subsystem_3 dev_uart_1
pm_add_requirement 0x1c000003 0x18224022 0x4 0x38
# subsystem_3 dev_gpio_pmc
pm_add_requirement 0x1c000003 0x1822402c 0x4 0xfffff
# subsystem_3 dev_swdt_fpd
pm_add_requirement 0x1c000003 0x18224029 0x4 0x38
# subsystem_3 dev_usb_0
pm_add_requirement 0x1c000003 0x18224018 0x4 0x38
# subsystem_3 dev_l2_bank_0
pm_add_requirement 0x1c000003 0x1831c00f 0x4 0xfffff
# subsystem_3 dev_ddr_0
pm_add_requirement 0x1c000003 0x18320010 0x4 0x38
# subsystem_3 dev_gpio
pm_add_requirement 0x1c000003 0x18224023 0x4 0xfffff
# subsystem_3 dev_ttc_0
pm_add_requirement 0x1c000003 0x18224024 0x4 0xfffff
# subsystem_3 dev_rtc
pm_add_requirement 0x1c000003 0x18224034 0x4 0xfffff
# subsystem_3 dev_adma_0
pm_add_requirement 0x1c000003 0x18224035 0x4 0xfffff
# subsystem_3 dev_adma_1
pm_add_requirement 0x1c000003 0x18224036 0x4 0xfffff
# subsystem_3 dev_adma_2
pm_add_requirement 0x1c000003 0x18224037 0x4 0xfffff
# subsystem_3 dev_adma_3
pm_add_requirement 0x1c000003 0x18224038 0x4 0xfffff
# subsystem_3 dev_adma_4
pm_add_requirement 0x1c000003 0x18224039 0x4 0xfffff
# subsystem_3 dev_adma_5
pm_add_requirement 0x1c000003 0x1822403a 0x4 0xfffff
# subsystem_3 dev_adma_6
pm_add_requirement 0x1c000003 0x1822403b 0x4 0xfffff
# subsystem_3 dev_adma_7
pm_add_requirement 0x1c000003 0x1822403c 0x4 0xfffff
# subsystem_3 dev_ipi_0
pm_add_requirement 0x1c000003 0x1822403d 0x8104 0xfffff
# subsystem_3 dev_ipi_1
pm_add_requirement 0x1c000003 0x1822403e 0x4 0xfffff
# subsystem_3 dev_ipi_2
pm_add_requirement 0x1c000003 0x1822403f 0x4 0xfffff
# subsystem_3 dev_ipi_3
pm_add_requirement 0x1c000003 0x18224040 0x4 0xfffff
# subsystem_3 dev_ipi_4
pm_add_requirement 0x1c000003 0x18224041 0x4 0xfffff
# subsystem_3 dev_ipi_5
pm_add_requirement 0x1c000003 0x18224042 0x4 0xfffff
# subsystem_3 dev_ipi_6
pm_add_requirement 0x1c000003 0x18224043 0x4 0xfffff
# subsystem_3 dev_tcm_0_a
pm_add_requirement 0x1c000003 0x1831800b 0x4 0xfffff
# subsystem_3 dev_tcm_0_b
pm_add_requirement 0x1c000003 0x1831800c 0x4 0xfffff
# subsystem_3 dev_tcm_1_a
pm_add_requirement 0x1c000003 0x1831800d 0x4 0xfffff
# subsystem_3 dev_tcm_1_b
pm_add_requirement 0x1c000003 0x1831800e 0x4 0xfffff
# subsystem_3 dev_uart_0
pm_add_requirement 0x1c000003 0x18224021 0x4 0x38
# subsystem_3 dev_qspi
pm_add_requirement 0x1c000003 0x1822402b 0x4 0xfffff
# subsystem_3 dev_aie
pm_add_requirement 0x1c000003 0x18224072 0x4 0xfffff
# subsystem_4 dev_rpu0_0
pm_add_requirement 0x1c000004 0x18110005 0x8104 0xfffff
# subsystem_4 dev_rtc
pm_add_requirement 0x1c000004 0x18224034 0x4 0xfffff
# subsystem_4 dev_tcm_0_a
pm_add_requirement 0x1c000004 0x1831800b 0x8304 0xfffff
# subsystem_4 dev_tcm_0_b
pm_add_requirement 0x1c000004 0x1831800c 0x8304 0xfffff
# subsystem_4 dev_tcm_1_a
pm_add_requirement 0x1c000004 0x1831800d 0x8304 0xfffff
# subsystem_4 dev_tcm_1_b
pm_add_requirement 0x1c000004 0x1831800e 0x8304 0xfffff
# subsystem_4 dev_swdt_fpd
pm_add_requirement 0x1c000004 0x18224029 0x4 0x6
# subsystem_4 dev_uart_1
pm_add_requirement 0x1c000004 0x18224022 0x8704 0x6
# subsystem_4 dev_ttc_2
pm_add_requirement 0x1c000004 0x18224026 0x4 0x1
# subsystem_4 dev_ipi_0
pm_add_requirement 0x1c000004 0x1822403d 0x4 0xfffff
# subsystem_4 dev_ipi_1
pm_add_requirement 0x1c000004 0x1822403e 0x8104 0xfffff
# subsystem_4 dev_ipi_2
pm_add_requirement 0x1c000004 0x1822403f 0x4 0xfffff
# subsystem_4 dev_ipi_3
pm_add_requirement 0x1c000004 0x18224040 0x4 0xfffff
# subsystem_4 dev_ipi_4
pm_add_requirement 0x1c000004 0x18224041 0x4 0xfffff
# subsystem_4 dev_ipi_5
pm_add_requirement 0x1c000004 0x18224042 0x4 0xfffff
# subsystem_4 dev_ipi_6
pm_add_requirement 0x1c000004 0x18224043 0x4 0xfffff
set_board custom
# Set clock Rate
pm_clock_set_rate 0x830c06a 0x1fc9f08
# TAMPER SETTINGS
# UNLOCKING SLCR
# PMC SLCR Write protection register for IO Muxes
mask_write 0xf1060828 0x1 0
# MIO
# Configures MIO Pin 0 peripheral interface mapping
mask_write 0xf1060000 0x3fe 0x6
# Configures MIO Pin 1 peripheral interface mapping
mask_write 0xf1060004 0x3fe 0x6
# Configures MIO Pin 2 peripheral interface mapping
mask_write 0xf1060008 0x3fe 0x6
# Configures MIO Pin 3 peripheral interface mapping
mask_write 0xf106000c 0x3fe 0x6
# Configures MIO Pin 4 peripheral interface mapping
mask_write 0xf1060010 0x3fe 0x6
# Configures MIO Pin 5 peripheral interface mapping
mask_write 0xf1060014 0x3fe 0x6
# Configures MIO Pin 6 peripheral interface mapping
mask_write 0xf1060018 0x3fe 0x6
# Configures MIO Pin 7 peripheral interface mapping
mask_write 0xf106001c 0x3fe 0x6
# Configures MIO Pin 8 peripheral interface mapping
mask_write 0xf1060020 0x3fe 0x6
# Configures MIO Pin 9 peripheral interface mapping
mask_write 0xf1060024 0x3fe 0x6
# Configures MIO Pin 10 peripheral interface mapping
mask_write 0xf1060028 0x3fe 0x6
# Configures MIO Pin 11 peripheral interface mapping
mask_write 0xf106002c 0x3fe 0x6
# Configures MIO Pin 12 peripheral interface mapping
mask_write 0xf1060030 0x3fe 0x6
# Configures MIO Pin 13 peripheral interface mapping
mask_write 0xf1060034 0x3fe 0x6
# Configures MIO Pin 14 peripheral interface mapping
mask_write 0xf1060038 0x3fe 0x6
# Configures MIO Pin 15 peripheral interface mapping
mask_write 0xf106003c 0x3fe 0x6
# Configures MIO Pin 16 peripheral interface mapping
mask_write 0xf1060040 0x3fe 0x6
# Configures MIO Pin 17 peripheral interface mapping
mask_write 0xf1060044 0x3fe 0x6
# Configures MIO Pin 18 peripheral interface mapping
mask_write 0xf1060048 0x3fe 0x6
# Configures MIO Pin 19 peripheral interface mapping
mask_write 0xf106004c 0x3fe 0x6
# Configures MIO Pin 20 peripheral interface mapping
mask_write 0xf1060050 0x3fe 0x6
# Configures MIO Pin 21 peripheral interface mapping
mask_write 0xf1060054 0x3fe 0x6
# Configures MIO Pin 22 peripheral interface mapping
mask_write 0xf1060058 0x3fe 0x6
# Configures MIO Pin 23 peripheral interface mapping
mask_write 0xf106005c 0x3fe 0x6
# Configures MIO Pin 24 peripheral interface mapping
mask_write 0xf1060060 0x3fe 0x6
# Configures MIO Pin 25 peripheral interface mapping
mask_write 0xf1060064 0x3fe 0x6
# Configures MIO Pin 26 peripheral interface mapping
mask_write 0xf1060068 0x3fe 0x2
# Configures MIO Pin 27 peripheral interface mapping
mask_write 0xf106006c 0x3fe 0x2
# Configures MIO Pin 28 peripheral interface mapping
mask_write 0xf1060070 0x3fe 0x2
# Configures MIO Pin 29 peripheral interface mapping
mask_write 0xf1060074 0x3fe 0x2
# Configures MIO Pin 30 peripheral interface mapping
mask_write 0xf1060078 0x3fe 0x2
# Configures MIO Pin 31 peripheral interface mapping
mask_write 0xf106007c 0x3fe 0x2
# Configures MIO Pin 32 peripheral interface mapping
mask_write 0xf1060080 0x3fe 0x2
# Configures MIO Pin 33 peripheral interface mapping
mask_write 0xf1060084 0x3fe 0x2
# Configures MIO Pin 34 peripheral interface mapping
mask_write 0xf1060088 0x3fe 0x2
# Configures MIO Pin 35 peripheral interface mapping
mask_write 0xf106008c 0x3fe 0x2
# Configures MIO Pin 36 peripheral interface mapping
mask_write 0xf1060090 0x3fe 0x2
# Configures MIO Pin 37 peripheral interface mapping
mask_write 0xf1060094 0x3fe 0x60
# Configures MIO Pin 39 peripheral interface mapping
mask_write 0xf106009c 0x3fe 0x8
# Configures MIO Pin 40 peripheral interface mapping
mask_write 0xf10600a0 0x3fe 0x180
# Configures MIO Pin 41 peripheral interface mapping
mask_write 0xf10600a4 0x3fe 0x180
# Configures MIO Pin 42 peripheral interface mapping
mask_write 0xf10600a8 0x3fe 0x40
# Configures MIO Pin 43 peripheral interface mapping
mask_write 0xf10600ac 0x3fe 0x40
# Configures MIO Pin 44 peripheral interface mapping
mask_write 0xf10600b0 0x3fe 0x80
# Configures MIO Pin 45 peripheral interface mapping
mask_write 0xf10600b4 0x3fe 0x80
# Configures MIO Pin 46 peripheral interface mapping
mask_write 0xf10600b8 0x3fe 0x80
# Configures MIO Pin 47 peripheral interface mapping
mask_write 0xf10600bc 0x3fe 0x80
# Configures MIO Pin 48 peripheral interface mapping
mask_write 0xf10600c0 0x3fe 0x60
# Configures MIO Pin 49 peripheral interface mapping
mask_write 0xf10600c4 0x3fe 0x60
# Configures MIO Pin 50 peripheral interface mapping
mask_write 0xf10600c8 0x3fe 0x100
# Configures MIO Pin 51 peripheral interface mapping
mask_write 0xf10600cc 0x3fe 0x2
# bnk0_en_wk_pu
mask_write 0xf1060114 0x3ffffff 0x3ffffff
# bnk1_en_wk_pu
mask_write 0xf1060314 0x2ffcfff 0x2ffc7ff
# bnk0_en_wk_pd
mask_write 0xf1060110 0x3ffffff 0
# bnk1_en_wk_pd
mask_write 0xf1060310 0x2ffcfff 0x800
# bnk0_sel_slew
mask_write 0xf1060120 0x3ffffff 0
# bnk1_sel_slew
mask_write 0xf1060320 0x2ffcfff 0
# bnk0_sel_drv0
mask_write 0xf1060118 0xffffffff 0xaaaaaaaa
# bnk0_sel_drv1
mask_write 0xf106011c 0xfffff 0xaaaaa
# bnk1_sel_drv0
mask_write 0xf1060318 0xf0ffffff 0xa0aaaaaa
# bnk1_sel_drv1
mask_write 0xf106031c 0xcffff 0x8aaaa
# bnk0_en_rx_schmitt_hyst
mask_write 0xf106010c 0x3ffffff 0x10030e1
# bnk1_en_rx_schmitt_hyst
mask_write 0xf106030c 0x2ffcfff 0x2024000
# MIO pin Tri-state Enables, 31:0
mask_write 0xf1060200 0x3ffffff 0x2840000
# MIO pin Tri-state Enables, 63:32
mask_write 0xf1060204 0x2ffcfff 0x18004
# LOCKING SLCR
# PMC SLCR Write protection register for IO Muxes
mask_write 0xf1060828 0x1 0x1
# PMCPLL INIT
# Helper data. Values are to be looked up in a table from Data Sheet
mask_write 0xf1260044 0xfe7fedef 0x7e5dcc6c
# UPDATE FB_DIV
# PLL Basic Control
mask_write 0xf1260040 0x73ff00 0x14800
# BY PASS PLL
# PLL Basic Control
mask_write 0xf1260040 0x8 0x8
# ASSERT RESET
# PLL Basic Control
mask_write 0xf1260040 0x1 0x1
# CLEAR ERROR STATUS AFTER RESET
# PMC Error Status Register. If any of the bits in this register is 1, it could generate any of the following events: (1) ERROR_OUT pin assertion, (2) POR, (3) IRQ to PPU1 MB, (4) SRST. Writing a 1 to any bit will clear the request. The register is only reset by the External Power-on Reset and maintains its state through a System Reset or Internal Power-on Reset.
mask_write 0xf1130004 0x1000000 0
# DEASSERT RESET
# PLL Basic Control
mask_write 0xf1260040 0x1 0
# CHECK PLL STATUS
mask_poll 0xf1260060 0x1 0x1 0x1000
# REMOVE PLL BY PASS
# PLL Basic Control
mask_write 0xf1260040 0x8 0
# Control for a clock that will be generated in the PMC, but used in the LPD/FPD as a clock source for the peripheral clock muxes.
mask_write 0xf1260100 0x3ff00 0x200
# NOCPLL INIT
# Helper data. Values are to be looked up in a table from Data Sheet
mask_write 0xf1260054 0xfe7fedef 0x7e4b0cac
# UPDATE FB_DIV
# PLL Basic Control
mask_write 0xf1260050 0x73ff00 0x27300
# BY PASS PLL
# PLL Basic Control
mask_write 0xf1260050 0x8 0x8
# ASSERT RESET
# PLL Basic Control
mask_write 0xf1260050 0x1 0x1
# CLEAR ERROR STATUS AFTER RESET
# PMC Error Status Register. If any of the bits in this register is 1, it could generate any of the following events: (1) ERROR_OUT pin assertion, (2) POR, (3) IRQ to PPU1 MB, (4) SRST. Writing a 1 to any bit will clear the request. The register is only reset by the External Power-on Reset and maintains its state through a System Reset or Internal Power-on Reset.
mask_write 0xf1130004 0x800000 0
# DEASSERT RESET
# PLL Basic Control
mask_write 0xf1260050 0x1 0
# CHECK PLL STATUS
mask_poll 0xf1260060 0x2 0x2 0x1000
# REMOVE PLL BY PASS
# PLL Basic Control
mask_write 0xf1260050 0x8 0
# Control for a clock that will be generated in the PMC, but used in the LPD/FPD as a clock source for the peripheral clock muxes.
mask_write 0xf1260104 0x3ff00 0x100
# PMC CLOCK CONTROL REGISTER
# This register controls this reference clock
mask_write 0xf1260108 0x203ff07 0x2000400
# This register controls this reference clock
mask_write 0xf1260148 0x203ff07 0x2002400
# This register controls this reference clock
mask_write 0xf126014c 0x203ff07 0x2000900
# This register controls this reference clock
mask_write 0xf1260114 0x203ff07 0x2000400
# This register controls this reference clock
mask_write 0xf1260118 0x103ff07 0x1000500
# This register controls this reference clock
mask_write 0xf126012c 0x103ff07 0x1000c00
# This register controls this reference clock
mask_write 0xf1260128 0x103ff07 0x1000600
# This register controls this reference clock
mask_write 0xf1260160 0x203ff07 0x2000100
# This register controls this reference clock
mask_write 0xf12605c0 0x103ff07 0x1000c00
# This register controls this reference clock
mask_write 0xf1260134 0x4 0
# This register controls this reference clock; This clock is not a PLL based clock. The input to this divider is IROCLK divide by 4.
mask_write 0xf1260140 0x3ff00 0x1f400
# This register controls this reference clock; This clock is not a PLL based clock. The input to this divider is IROCLK divide by 4.
mask_write 0xf1260144 0x3ff00 0x6400
# PMC SEM CONTROL REGISTER
# Register block that holds the configuration of the SEM function that scans CRAM.
mask_write 0xf1111000 0xb 0
# Register block that holds the configuration of the SEM function that scans NPI registers.
mask_write 0xf1111004 0x3ff03 0
# ROOT SYSMON PROGRAMMING
# PUT SYMON IN RESET
# Reset for Individual block
mask_write 0xf126032c 0x1 0x1
# SWITCHING SYSMON CLOCK
# This register controls this reference clock
mask_write 0xf1260138 0x4 0x4
# RELEASE SYSMON RESET
# Reset for Individual block
mask_write 0xf126032c 0x1 0
# PMC_SYSMON_SAT0
# UNLOCK PMC SYSMON SAT0
# NPI Lock Register
write 0xf128000c 0xf9e8d7c6
# PMC SYSMON SAT0 BASE CONFIGURATION
# DMA WRITE 1
write 0xf1280100 0xff
write 0xf1280104 0x1f1d77
write 0xf1280108 0xf
write 0xf128010c 0x2128
write 0xf1280110 0x2
write 0xf1280114 0x1
write 0xf1280124 0xdcdc2321 0x2de 0 0 0x60524 0x60 0x1bd6446 0x10624d 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
# DMA WRITE 2
write 0xf1280188 0
write 0xf128018c 0
write 0xf1280190 0
write 0xf1280194 0
write 0xf1280198 0
write 0xf128019c 0
write 0xf12801a0 0
write 0xf1280500 0 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0 0 0
write 0xf128011c 0x4
write 0xf1280120 0
write 0xf1280118 0x4f
# SAT0 PCSR END SEQUENCE
# GATEREG DEASSERT
# Programming Mask Register
write 0xf1280000 0x2
# Programming Control Register
write 0xf1280004 0
# INITSTATE DEASSERT
# Programming Mask Register
write 0xf1280000 0x40
# Programming Control Register
write 0xf1280004 0
# HOLDSTATE DE-ASSERTED AND PCOMPLETE ASSERTED IN AMS SATELLITES.
# Programming Mask Register
write 0xf1280000 0x81
# Programming Control Register
write 0xf1280004 0x1
# LOCK PMC SYSMON SAT0
# NPI Lock Register
write 0xf128000c 0x1
# PMC_SYSMON_SAT1
# UNLOCK PMC SYSMON SAT1
# NPI Lock Register
write 0xf129000c 0xf9e8d7c6
# PMC SYSMON SAT1 BASE CONFIGURATION
# DMA WRITE 1
write 0xf1290100 0xff
write 0xf1290104 0x1f1d77
write 0xf1290108 0xf
write 0xf129010c 0x2128
write 0xf1290110 0x2
write 0xf1290114 0x1
write 0xf1290124 0xdcdc2321 0x2de 0 0 0x60524 0x60 0x1bd6446 0x10624d 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
# DMA WRITE 2
write 0xf1290188 0
write 0xf129018c 0
write 0xf1290190 0
write 0xf1290194 0
write 0xf1290198 0
write 0xf129019c 0
write 0xf12901a0 0
write 0xf1290500 0 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0x28000000 0 0 0
write 0xf129011c 0x45
write 0xf1290120 0x4
write 0xf1290118 0x4f
# SAT1 PCSR END SEQUENCE
# GATEREG DEASSERT
# Programming Mask Register
write 0xf1290000 0x2
# Programming Control Register
write 0xf1290004 0
# INITSTATE DEASSERT
# Programming Mask Register
write 0xf1290000 0x40
# Programming Control Register
write 0xf1290004 0
# HOLDSTATE DE-ASSERTED AND PCOMPLETE ASSERTED IN AMS SATELLITES.
# Programming Mask Register
write 0xf1290000 0x81
# Programming Control Register
write 0xf1290004 0x1
# LOCK PMC SYSMON SAT1
# NPI Lock Register
write 0xf129000c 0x1
# UNLOCK PMC SYSMON
# NPI Lock Register
write 0xf127000c 0xf9e8d7c6
# DEFAULT ROOT PROGRAMMING
# Description
write 0xf1270100 0x10000
# Description
mask_write 0xf1270104 0x1fffff 0x1c00ff
# Description
write 0xf1270108 0x440
# Description
write 0xf127010c 0x880
# Description
write 0xf1270110 0xcc0
# Description
write 0xf1270114 0x1100
# Description
write 0xf1270118 0
# Description
write 0xf127011c 0
# Description
write 0xf1270124 0
# Description
write 0xf1270128 0
# Description
write 0xf1270134 0
# Description
write 0xf1270138 0
# Description
write 0xf127013c 0
# Description
write 0xf127015c 0
# Description
write 0xf127017c 0
# Description
write 0xf1270180 0
# Description
write 0xf1270184 0
# Description
write 0xf1270188 0
# DMA WRITE
write 0xf1271940 0
write 0xf1271944 0
write 0xf1271948 0
write 0xf127194c 0
write 0xf1271950 0
write 0xf1271958 0
write 0xf127195c 0
write 0xf1271960 0
write 0xf1271964 0
write 0xf1271968 0
write 0xf1271970 0
write 0xf1271974 0x3e80
write 0xf1271978 0
write 0xf127197c 0x3e80
write 0xf1271980 0
write 0xf1271c80 0
write 0xf1271984 0
write 0xf1271c84 0
write 0xf1271988 0
write 0xf1271c88 0
write 0xf127198c 0
write 0xf1271c8c 0
write 0xf1271990 0
write 0xf1271c90 0
write 0xf1271994 0
write 0xf1271c94 0
write 0xf1271998 0
write 0xf1271c98 0
write 0xf127199c 0
write 0xf1271c9c 0
write 0xf12719a0 0
write 0xf1271ca0 0
write 0xf12719a4 0
write 0xf1271ca4 0
write 0xf12719a8 0
write 0xf1271ca8 0
write 0xf12719ac 0
write 0xf1271cac 0
write 0xf12719b0 0
write 0xf1271cb0 0
write 0xf12719b4 0
write 0xf1271cb4 0
write 0xf12719b8 0
write 0xf1271cb8 0
write 0xf12719bc 0
write 0xf1271cbc 0
write 0xf12719c0 0
write 0xf1271cc0 0
write 0xf12719c4 0
write 0xf1271cc4 0
write 0xf12719c8 0
write 0xf1271cc8 0
write 0xf12719cc 0
write 0xf1271ccc 0
write 0xf12719d0 0
write 0xf1271cd0 0
write 0xf12719d4 0
write 0xf1271cd4 0
write 0xf12719d8 0
write 0xf1271cd8 0
write 0xf12719dc 0
write 0xf1271cdc 0
write 0xf12719e0 0
write 0xf1271ce0 0
write 0xf12719e4 0
write 0xf1271ce4 0
write 0xf12719e8 0
write 0xf1271ce8 0
write 0xf12719ec 0
write 0xf1271cec 0
write 0xf12719f0 0
write 0xf1271cf0 0
write 0xf12719f4 0
write 0xf1271cf4 0
write 0xf12719f8 0
write 0xf1271cf8 0
write 0xf12719fc 0
write 0xf1271cfc 0
write 0xf1271a00 0
write 0xf1271d00 0
write 0xf1271a04 0
write 0xf1271d04 0
write 0xf1271a08 0
write 0xf1271d08 0
write 0xf1271a0c 0
write 0xf1271d0c 0
write 0xf1271a10 0
write 0xf1271d10 0
write 0xf1271a14 0
write 0xf1271d14 0
write 0xf1271a18 0
write 0xf1271d18 0
write 0xf1271a1c 0
write 0xf1271d1c 0
write 0xf1271a20 0
write 0xf1271d20 0
write 0xf1271a24 0
write 0xf1271d24 0
write 0xf1271a28 0
write 0xf1271d28 0
write 0xf1271a2c 0
write 0xf1271d2c 0
write 0xf1271a30 0
write 0xf1271d30 0
write 0xf1271a34 0
write 0xf1271d34 0
write 0xf1271a38 0
write 0xf1271d38 0
write 0xf1271a3c 0
write 0xf1271d3c 0
write 0xf1271a40 0
write 0xf1271d40 0
write 0xf1271a44 0
write 0xf1271d44 0
write 0xf1271a48 0
write 0xf1271d48 0
write 0xf1271a4c 0
write 0xf1271d4c 0
write 0xf1271a50 0
write 0xf1271d50 0
write 0xf1271a54 0
write 0xf1271d54 0
write 0xf1271a58 0
write 0xf1271d58 0
write 0xf1271a5c 0
write 0xf1271d5c 0
write 0xf1271a60 0
write 0xf1271d60 0
write 0xf1271a64 0
write 0xf1271d64 0
write 0xf1271a68 0
write 0xf1271d68 0
write 0xf1271a6c 0
write 0xf1271d6c 0
write 0xf1271a70 0
write 0xf1271d70 0
write 0xf1271a74 0
write 0xf1271d74 0
write 0xf1271a78 0
write 0xf1271d78 0
write 0xf1271a7c 0
write 0xf1271d7c 0
write 0xf1271a80 0
write 0xf1271d80 0
write 0xf1271a84 0
write 0xf1271d84 0
write 0xf1271a88 0
write 0xf1271d88 0
write 0xf1271a8c 0
write 0xf1271d8c 0
write 0xf1271a90 0
write 0xf1271d90 0
write 0xf1271a94 0
write 0xf1271d94 0
write 0xf1271a98 0
write 0xf1271d98 0
write 0xf1271a9c 0
write 0xf1271d9c 0
write 0xf1271aa0 0
write 0xf1271da0 0
write 0xf1271aa4 0
write 0xf1271da4 0
write 0xf1271aa8 0
write 0xf1271da8 0
write 0xf1271aac 0
write 0xf1271dac 0
write 0xf1271ab0 0
write 0xf1271db0 0
write 0xf1271ab4 0
write 0xf1271db4 0
write 0xf1271ab8 0
write 0xf1271db8 0
write 0xf1271abc 0
write 0xf1271dbc 0
write 0xf1271ac0 0
write 0xf1271dc0 0
write 0xf1271ac4 0
write 0xf1271dc4 0
write 0xf1271ac8 0
write 0xf1271dc8 0
write 0xf1271acc 0
write 0xf1271dcc 0
write 0xf1271ad0 0
write 0xf1271dd0 0
write 0xf1271ad4 0
write 0xf1271dd4 0
write 0xf1271ad8 0
write 0xf1271dd8 0
write 0xf1271adc 0
write 0xf1271ddc 0
write 0xf1271ae0 0
write 0xf1271de0 0
write 0xf1271ae4 0
write 0xf1271de4 0
write 0xf1271ae8 0
write 0xf1271de8 0
write 0xf1271aec 0
write 0xf1271dec 0
write 0xf1271af0 0
write 0xf1271df0 0
write 0xf1271af4 0
write 0xf1271df4 0
write 0xf1271af8 0
write 0xf1271df8 0
write 0xf1271afc 0
write 0xf1271dfc 0
write 0xf1271b00 0
write 0xf1271e00 0
write 0xf1271b04 0
write 0xf1271e04 0
write 0xf1271b08 0
write 0xf1271e08 0
write 0xf1271b0c 0
write 0xf1271e0c 0
write 0xf1271b10 0
write 0xf1271e10 0
write 0xf1271b14 0
write 0xf1271e14 0
write 0xf1271b18 0
write 0xf1271e18 0
write 0xf1271b1c 0
write 0xf1271e1c 0
write 0xf1271b20 0
write 0xf1271e20 0
write 0xf1271b24 0
write 0xf1271e24 0
write 0xf1271b28 0
write 0xf1271e28 0
write 0xf1271b2c 0
write 0xf1271e2c 0
write 0xf1271b30 0
write 0xf1271e30 0
write 0xf1271b34 0
write 0xf1271e34 0
write 0xf1271b38 0
write 0xf1271e38 0
write 0xf1271b3c 0
write 0xf1271e3c 0
write 0xf1271b40 0
write 0xf1271e40 0
write 0xf1271b44 0
write 0xf1271e44 0
write 0xf1271b48 0
write 0xf1271e48 0
write 0xf1271b4c 0
write 0xf1271e4c 0
write 0xf1271b50 0
write 0xf1271e50 0
write 0xf1271b54 0
write 0xf1271e54 0
write 0xf1271b58 0
write 0xf1271e58 0
write 0xf1271b5c 0
write 0xf1271e5c 0
write 0xf1271b60 0
write 0xf1271e60 0
write 0xf1271b64 0
write 0xf1271e64 0
write 0xf1271b68 0
write 0xf1271e68 0
write 0xf1271b6c 0
write 0xf1271e6c 0
write 0xf1271b70 0
write 0xf1271e70 0
write 0xf1271b74 0
write 0xf1271e74 0
write 0xf1271b78 0
write 0xf1271e78 0
write 0xf1271b7c 0
write 0xf1271e7c 0
write 0xf1271b80 0
write 0xf1271e80 0
write 0xf1271b84 0
write 0xf1271e84 0
write 0xf1271b88 0
write 0xf1271e88 0
write 0xf1271b8c 0
write 0xf1271e8c 0
write 0xf1271b90 0
write 0xf1271e90 0
write 0xf1271b94 0
write 0xf1271e94 0
write 0xf1271b98 0
write 0xf1271e98 0
write 0xf1271b9c 0
write 0xf1271e9c 0
write 0xf1271ba0 0
write 0xf1271ea0 0
write 0xf1271ba4 0
write 0xf1271ea4 0
write 0xf1271ba8 0
write 0xf1271ea8 0
write 0xf1271bac 0
write 0xf1271eac 0
write 0xf1271bb0 0
write 0xf1271eb0 0
write 0xf1271bb4 0
write 0xf1271eb4 0
write 0xf1271bb8 0
write 0xf1271eb8 0
write 0xf1271bbc 0
write 0xf1271ebc 0
write 0xf1271bc0 0
write 0xf1271ec0 0
write 0xf1271bc4 0
write 0xf1271ec4 0
write 0xf1271bc8 0
write 0xf1271ec8 0
write 0xf1271bcc 0
write 0xf1271ecc 0
write 0xf1271bd0 0
write 0xf1271ed0 0
write 0xf1271bd4 0
write 0xf1271ed4 0
write 0xf1271bd8 0
write 0xf1271ed8 0
write 0xf1271bdc 0
write 0xf1271edc 0
write 0xf1271be0 0
write 0xf1271ee0 0
write 0xf1271be4 0
write 0xf1271ee4 0
write 0xf1271be8 0
write 0xf1271ee8 0
write 0xf1271bec 0
write 0xf1271eec 0
write 0xf1271bf0 0
write 0xf1271ef0 0
write 0xf1271bf4 0
write 0xf1271ef4 0
write 0xf1271bf8 0
write 0xf1271ef8 0
write 0xf1271bfc 0
write 0xf1271efc 0
write 0xf1271f80 0
write 0xf1271f84 0
write 0xf1271f9c 0
write 0xf1271fa0 0
write 0xf12724b4 0xffffffff
write 0xf12724b8 0xffffffff
# ROOT SYSMON CONFIGURATION
# Description
mask_write 0xf1271970 0xffff 0
# Description
mask_write 0xf1271974 0xffff 0x3e80
# Description
mask_write 0xf127197c 0xffff 0x3e80
# Description
mask_write 0xf1271978 0xffff 0xe480
# Description
mask_write 0xf1271f84 0x3 0
# Description
mask_write 0xf1270100 0xf83c000 0x4800000
# Description
mask_write 0xf1270120 0x200 0x200
# ROOT PCSR END SEQUENCE
# GATEREG DEASSERT
# Programming Mask Register
write 0xf1270000 0x2
# Programming Control Register
write 0xf1270004 0
# INITSTATE DEASSERT
# Programming Mask Register
write 0xf1270000 0x40
# Programming Control Register
write 0xf1270004 0
# ODISABLE DE-ASSERTED AND PCOMPLETE ASSERTED IN AMS ROOT.
# Programming Mask Register
write 0xf1270000 0x3d
# Programming Control Register
write 0xf1270004 0x1
# BRING ROOT OUT OF RESET
# Programming Mask Register
write 0xf1270000 0x41
# Programming Control Register
write 0xf1270004 0x1
# START ROOT CALIBRATION
# Programming Mask Register
write 0xf1270000 0x400
# Programming Control Register
write 0xf1270004 0x400
# LOCK PMC SYSMON
# NPI Lock Register
write 0xf127000c 0x1
# SD1 BASE CLOCK
# SD Config Register 1
mask_write 0xf1060490 0x7f80 0x6400
# SoC Debug Clock Control
mask_write 0xf1060480 0x1 0x1
# SD1 DLL DIV MAP
# SDIO DLL Divider Mapping wrt sd_ref_clk Divider
mask_write 0xf10604d8 0xffffffff 0x4830180c
# SD1
# SD eMMC selection
mask_write 0xf1060484 0x1 0
# SD Config Register 2
mask_write 0xf1060494 0x3380 0x280
# SD1 RETUNER
# SD Config Register 3
mask_write 0xf1060498 0x3c0 0
# SD1 RESET RELESE
# Reset for Individual block
mask_write 0xf126030c 0x1 0
# USB PHY RESET RELESE
# Reset for Individual block
mask_write 0xf1260334 0x1 0
# QSPI RESET RELESE
# Reset for Individual block
mask_write 0xf1260300 0x1 0
# GPIO RESET RELESE
# Reset for Individual block
mask_write 0xf1260318 0x1 0
# PMC MUX/DEMUX FOR HSDP
# DPC mux select register
mask_write 0xf11a0020 0x3 0
# QSPI OSPI CONFIGURATION
# MUX selects for AXI slaves
mask_write 0xf1060504 0x1 0
# COHERENCY
# GPIO PROGRAMMING
# DIR MODE BANK 0
# Direction mode (GPIO Bank0, MIO)
mask_write 0xf1020204 0x3ffffff 0
# DIR MODE BANK 1
# Direction mode (GPIO Bank1, MIO)
mask_write 0xf1020244 0x3ffffff 0xc00800
# OUTPUT ENABLE BANK 0
# Output enable (GPIO Bank0, MIO)
mask_write 0xf1020208 0x3ffffff 0
# OUTPUT ENABLE BANK 1
# Output enable (GPIO Bank1, MIO)
mask_write 0xf1020248 0x3ffffff 0xc00800
# MASK_DATA_0_LSW LOW BANK [15:0]
# Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
mask_write 0xf1020000 0xffffffff 0xffff0000
# MASK_DATA_0_MSW LOW BANK [25:16]
# Maskable Output Data (GPIO Bank0, MIO, Upper 10bits)
mask_write 0xf1020004 0x3ff03ff 0x3ff0000
# MASK_DATA_1_LSW LOW BANK [41:26]
# Maskable Output Data (GPIO Bank1, MIO, Lower 16bits)
mask_write 0xf1020008 0xffffffff 0xf7ff0800
# MASK_DATA_1_MSW HIGH BANK [51:42]
# Maskable Output Data (GPIO Bank1, MIO, Upper 10 bits)
mask_write 0xf102000c 0x3ff03ff 0x3ff0000