This page provides an overview of the 2020.2 version of the Zynq UltraScale+ MPSoC VCU TRD.  This TRD is made up of several design modules.  A description of the design modules and links to the individual design module pages can be found in the Design Modules below.

This page complements the TRD User Guide: UG1250

Table of Contents

1 Revision History

Change Log:

• Updated all projects, IPs, and tools versions to 2020.2

• Updated Vivado HLS IPs to Vitis HLS IPs in all designs

• Updated PL DDR HDMI design with single-stream HDR10 support

• Updated PL DDR SDI design with initial 8 channel Audio support

• Added support for Quad Sensor MIPI CSI design using Avnet Quad Camera FMC module

• Added support for different XAVC standards compliance profiles

• Added AXI4-Stream Broadcaster driver instead of dummy driver for multi-stream HDMI use-cases

2 Overview

This is the main page of VCU TRD wiki, which has links to redirect wiki pages corresponding to individual design modules. It also explains the complete feature list and the supported resources of all the designs. TRD package web link is provided for the user to download. This page also gives information on required software tools, IP licenses.

The Zynq® UltraScale+™ MPSoC Video Codec Unit (VCU) Targeted Reference Design (TRD) consists of an embedded video encoding/decoding application that runs on the Processing System (PS). The overall functionality of the TRD is partitioned between the Processing System (PS), Video Codec Unit, and Programmable Logic (PL) for optimal performance. 

The primary goal of this TRD is to demonstrate the capabilities of the VCU core which is an integrated hard block present in Zynq UltraScale+ MPSoC EV devices. The TRD serves as a platform for the user to tune the performance parameters of VCU and arrives at an optimal configuration for encoder and decoder blocks for their specific use