This page is broken into 2 sections. The first is example designs. An example design is a design that is in a point in time. Meaning done on a Xilinx tool release and not necessarially updated. If the user wants this design example they can use it on the tool release it was created on or take on porting to the desired tool release on their own. The second section are Targeted Reference Designs or TRDs. These designed are updated on each major tool release for a set amount of time. The TRDs are better supported than the example designs.
Targeted Reference Designs (TRDs)
- Zynq UltraScale MPSoC Software Acceleration TRD 2016.2
- Zynq UltraScale+ MPSoC Base TRD 2016.1
- Zynq UltraScale+ MPSoC Base TRD 2016.2
- Zynq UltraScale+ MPSoC Base TRD 2016.3
- Zynq UltraScale+ MPSoC Base TRD 2016.4
- Zynq UltraScale+ MPSoC Base TRD 2017.1
- Zynq UltraScale+ MPSoC Base TRD 2017.2
- Zynq UltraScale+ MPSoC Base TRD 2017.4
- Zynq UltraScale+ MPSoC Base TRD 2018.1
- Zynq UltraScale+ MPSoC Base TRD 2018.2
- Zynq UltraScale+ MPSoC Base TRD 2018.2
- Zynq UltraScale+ MPSoC Base TRD 2018.3
- Zynq UltraScale+ MPSoC Software Acceleration TRD 2016.1
- Zynq UltraScale+ MPSoC Software Acceleration TRD 2018.1
- Zynq UltraScale+ MPSoC VCU TRD 2018.1
- Zynq UltraScale+ MPSoC VCU TRD 2018.2
- Zynq UltraScale+ MPSoC VCU TRD 2018.3