This wiki page complements the 2018.2 version of the VCU TRD.
Updated all projects, IPs, and tools versions to 2018.2
Frame-drops fixed in 4Kp60 AVC pipeline till 60 Mbps.
The Zynq® UltraScale+™ MPSoC Video Codec Unit (VCU) Targeted Reference Design (TRD) consists of an embedded video encoding/decoding application that runs on the Processing System (PS). Overall functionality of the TRD is partitioned between the Processing System (PS), Video Codec Unit, and Programmable Logic (PL) for optimal performance. The below figure shows the TRD block diagram. It consists of four Design Modules (DM1, DM2, DM3, DM4). The components of each design module are highlighted in unique colors in the diagram. The remaining blocks are common to all design modules as shown.
The primary goal of this TRD is to demonstrate the capabilities of the VCU core which is an integrated hard block present in Zynq UltraScale+ MPSoC EV devices. The TRD serves as a platform for the user to tune the performance parameters of VCU and arrives at an optimal configuration for encoder and decoder blocks for their specific use case. The TRD uses Vivado IP Integrator (IPI) flow for building the hardware design and Xilinx Yocto PetaLinux flow for software design. It uses Xilinx IPs and software drivers to demonstrate the capabilities of different components. The TRD consists of four design-modules described in section 4.1.
The TRD supports the following video interfaces:
Test pattern generator (TPG) implemented in the PL.
HDMI-Rx capture pipeline implemented in the PL.
MIPI CSI-2 Rx capture pipeline implemented in the PL.
File source (SD card, USB storage, SATA hard disk).
SDI-Rx capture pipeline implemented in the PL.
DP Tx display pipeline in the PS.
HDMI-Tx display pipeline implemented in the PL.
SDI-Tx display pipeline implemented in the PL.
This tutorial contains information about:
How to set up the ZCU106 evaluation board and run the TRD.
How to build all the TRD components via detailed step-by-step tutorials.
ZCU106 rev B/C/D/E/F/1.0: including all source code and project files.
3.3 Download, Installation, and Licensing
The Vivado Design Suite User Guide explains how to download and install the Vivado® Design Suite tools, which includes the Vivado Integrated Design Environment (IDE), High-Level Synthesis tool, and System Generator for DSP. This guide also provides the information about licensing and administering evaluation and full copies of Xilinx design tools and intellectual property (IP) products. The Vivado Design Suite can be downloaded from here.
LogiCORE IP Licensing
The following IP cores require a license to build the design.
The TRD package is released with the source code, Vivado project, petalinux project, and SD card image that enables the user to run the demonstration. It also includes the binaries necessary to configure and boot the ZCU106 board. Prior to running the steps mentioned in this wiki page, download the TRD package and extract its contents to a directory referred to as ‘TRD_HOME' which is the home directory.
For the individual tutorials on each design module, follow the links below:
No overlapping issue with 4kp30 and 1080p60 pipeline.
SDI-Tx link up issue is observed after booting in SDI design.
Workaround: Re-launch the modetest by running “$ source /media/card/autostart.sh” from the command line.
TRD supports 4kp and 1080p resolutions output sink.
All VCU parameters are not exposed at GStreamer.
This design is validated with HDMI sources (ABOX/Nvidia shield Pro) and DP/HDMI-Tx monitors that are mentioned earlier in the compatibility section. Other sources may or may not work with the TRD out of the box.
In HEVC/AVC, max supported bitrate is 60Mbps for a single pipeline.
To achieve reliable total aggregate 4kp60 system bandwidth (1x4kp60 Or 2x4kp30 Or 4x1080p60 pipelines) b-frames should be 0, l2-cache should be enabled, gop-mode should be either basic or low_delay_p and aggregate bitrate should be 60Mbps due to bandwidth constraints.
TRD is tested only with MONOPRICE 1x4HDMI Splitter which works up to 4kp30.
This design is validated with Teranex Mini HDMI to SDI 12G and SDI to HDMI 12G , that are mentioned earlier in the compatibility section.
Support for only Single stream playback from the command line is available with SDI Design.
In DP for File playback, video file resolution should match to DP's native resolution.
To obtain technical support for this reference design, go to the:
Xilinx Community Forums to ask questions or discuss technical details and issues. Please make sure to browse the existing topics first before filing a new topic. If you do file a new topic, make sure it is filed in the sub-forum that best describes your issue or question e.g. Embedded Linux for any Linux related questions. Please include "ZCU106 VCU TRD" and the release version in the topic name along with a brief summary of the issue.