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Sr No. | Clock Names | Clock Frequencies | Notes |
| 1 | DAC# Analog Clock (PCB) | 245.76 MHz | Sampling rate selected is 3.93216 GSPS for xczu29dr and 4.42368 GSPS for xczu39dr |
| 2 | ADC# Analog Clock (PCB) | 245.76 MHz | Sampling rate selected is 1.96608 GSPS for xczu29dr and 2.21184 GSPS for xczu39dr |
| 3 | PL REF CLK (PCB) | 122.88 MHz | |
| 4 | SYSREF (PCB) | 7.68 MHz | |
| 5 | PL SYSREF (PCB) | 7.68 MHz |
DAC Clocking
ADC Clocking
There is a common trigger signal for all channels so that all 16-channels are triggered as the same instant. These triggers are enabled by using channel control GPIO pins. As can be seen in figures above the common trigger from GPIO is synchronized in to DAC and ADC clock domains before being applied to fabric design.
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