This page provides all the information related to Design Module 12 - VCU TRD Xilinx low latency(LLP2) PL DDR HDMI design.
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For Petalinux related known issues please refer: PetaLinux 2021.2 - Product Update Release Notes and Known Issues
For VCU related known issues please refer AR# 76600: LogiCORE H.264/H.265 Video Codec Unit (VCU) - Release Notes and Known Issues and Xilinx Zynq UltraScale+ MPSoC Video Codec Unit.
To reduce performance issues with llp2 4x serial pipelines, please refer to chapter# 40 of Section VI: Appendices for IRQ Balancing schemein PG252.
2.2 Limitations
For Petalinux related limitations please refer: PetaLinux 2021.2 - Product Update Release Notes and Known Issues
For VCU related limitations please refer AR# 76600: LogiCORE H.264/H.265 Video Codec Unit (VCU) - Release Notes and Known Issues, Xilinx Zynq UltraScale+ MPSoC Video Codec Unit and PG252.
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Pixel Format | GStreamer Format | Media Bus Format | GStreamer HEVC Profile | GStreamer AVC Profile | Kmssink Plane-id |
|---|---|---|---|---|---|
XV20 | NV16_10LE32 | UYVY10_1X20 | main-422-10 | high-4:2:2 | 34 and 35 |
NV16 | NV16 | UYVY8_1X16 | main-422 | high-4:2:2 | 36 and 37 |
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