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Zynq UltraScale+ MPSoC VCU TRD 2018.2

Table of Contents

Table of Contents

1 Revision History

This wiki page complements the 2018.2 version of the VCU TRD.

Change Log:
  • Updated all projects, IPs, and tools versions to 2018.2
  • Frame-drops fixed in 4Kp60 AVC pipeline till 60 Mbps.

2 Overview

The Zynq® UltraScale+™ MPSoC Video Codec Unit (VCU) Targeted Reference Design (TRD) consists of an embedded video encoding/decoding application that runs on the Processing System (PS). Overall functionality of the TRD is partitioned between the Processing System (PS), Video Codec Unit, and Programmable Logic (PL) for optimal performance. The below figure shows the TRD block diagram. It consists of four Design Modules (DM1, DM2, DM3, DM4). The components of each design module are highlighted in unique colors in the diagram. The remaining blocks are common to all design modules as shown.

The primary goal of this TRD is to demonstrate the capabilities of the VCU core which is an integrated hard block present in Zynq UltraScale+ MPSoC EV devices. The TRD serves as a platform for the user to tune the performance parameters of VCU and arrives at an optimal configuration for encoder and decoder blocks for their specific use case. The TRD uses Vivado IP Integrator (IPI) flow for building the hardware design and Xilinx Yocto PetaLinux flow for software design. It uses Xilinx IPs and software drivers to demonstrate the capabilities of different components. The TRD consists of four design-modules described in section 4.1.

The TRD supports the following video interfaces:

  • Test pattern generator (TPG) implemented in the PL.
  • HDMI-Rx capture pipeline implemented in the PL.
  • MIPI CSI-2 Rx capture pipeline implemented in the PL.
  • File source (SD card, USB storage, SATA hard disk).
  • SDI-Rx capture pipeline implemented in the PL.
  • DP Tx display pipeline in the PS.
  • HDMI-Tx display pipeline implemented in the PL.
  • SDI-Tx display pipeline implemented in the PL.

This tutorial contains information about:
  • How to set up the ZCU106 evaluation board and run the TRD.
  • How to build all the TRD components via detailed step-by-step tutorials.

Additional material available for reference:

3 Software Tools and System Requirements

3.1 Hardware

  • ZCU106 evaluation board (rev B/C/D/E/F/1.0) with power cable
  • Monitor with DisplayPort/HDMI input supporting 3840x2160 resolution
  • Display Port cable (DP certified)
  • HDMI cable
  • Class-10 SD card
  • GooBang Doo ABOX 2017 player with the resolution set to 4KP30, color space to VUY24 and HDMI cable
  • USB mouse
  • Ethernet cable
  • SDI Receiver - Black Magic Teranex Mini HDMI to 12G converter
  • SDI Transmitter - Black Magic Teranex Mini 12G to HDMI converter


3.2 Software


3.3 Download, Installation, and Licensing

The Vivado Design Suite User Guide explains how to download and install the Vivado® Design Suite tools, which includes the Vivado Integrated Design Environment (IDE), High-Level Synthesis tool, and System Generator for DSP. This guide also provides the information about licensing and administering evaluation and full copies of Xilinx design tools and intellectual property (IP) products. The Vivado Design Suite can be downloaded from here.

LogiCORE IP Licensing

The following IP cores require a license to build the design.

To obtain the LogiCORE IP license, please visit the respective IP product page and get the license.

3.4 Compatibility

The reference design has been tested successfully with the following user-supplied components.

DisplayPort Monitor:
Make/ModelNative Resolution
Viewsonic VX2475SMHL-4K (VS16024)3840x2160 (30Hz)
LG 27MU67-B3840x2160 (30Hz)

HDMI Monitor:
LG 27UD883840x2160 (30Hz)
Philips BDM4350UC3840 x 2160 @ 60Hz

HDMI Input Sources:
  • GooBang Doo ABOX 2017 player

DisplayPort Cable:
  • Cable Matters DisplayPort Cable-E342987
  • Monster Advanced DisplayPort Cable-E194698
  • HDMI 2.0 compatible cable

4 Design Files

4.1 Design Modules

The TRD consists of four designs which are highlighted in four colors as shown in the above figure.

The following table shows the dependency matrix between different modules. For example: DM4 (row) depends on or builds on top of modules DM1.




4.2 Download the TRD

The TRD has been tested on Rev B, Rev C, Rev D, Rev E, Rev F and Rev 1.0 ZCU106 evaluation boards with Production silicon. The following design files can be downloaded from here.

4.3 TRD Directory Structure and Package Contents

The TRD package is released with the source code, Vivado project, petalinux project, and SD card image that enables the user to run the demonstration. It also includes the binaries necessary to configure and boot the ZCU106 board. Prior to running the steps mentioned in this wiki page, download the TRD package and extract its contents to a directory referred to as ‘TRD_HOME' which is the home directory.

5 Tutorials

For the individual tutorials on each design module, follow the links below:

The table below lists the available hardware projects and the script used to generate them. These can be found in the scripts folder in package under "pl/scripts".
ModuleProject NameScript NameDescription
DM1HDMIRX + VCUhdmirx_proj.tclVCU based mini reference design showcasing HDMI receive along VCU capabilities of ZCU106 & MPSoC
DM2SDIRX + VCUsdirx_proj.tclVCU based mini reference design showcasing SDI receive and VCU capabilities of ZCU106 & MPSoC
DM3SDIRX + VCU + SDITXsdirxtx_proj.tclVCU based video design showcasing SDI receive and SDI transmit capabilities of ZCU106 board
DM4VCU TRDvcu_trd_proj.tclMulti stream VCU TRD design supporting 3 video pipelines (HDMI, TPG & MIPI)

6 Other Information

6.1 Known Issues

  • Block noise is observed with CBR at lower bitrates(<30Mbps with AVC and < 10Mbps with HEVC) in 4kp60/4kp30.
    • Frequency: Always
    • Workaround: User can run with the bitrate of 30-60 Mbps in CBR rate control mode to avoid block noise.
  • Reduced/sub-frame latency mode is not fully functional at all resolutions 4kp60/4kp30/1080p60. Observing frame drops and pipeline doesn't exit gracefully.
    • Frequency: Always
    • Workaround: None.
NOTE: TRD has been tested with normal latency mode and it's working fine. Reduced/sub_frame latency mode is disabled in GUI but, enabled in cmd line app for user experience.
  • TPG is not supported in the 1080p mode. 4kp30 and 4kp60 modes are working fine.
    • Frequency: Always
    • Workaround: None.
  • Stopping record pipeline earlier than the chosen time limit (1/2/3 Minutes) will create an invalid stream.
    • Frequency: Always
    • Workaround: Run the record pipeline until the time limit.
  • Flickering, block noise and frame drop observed with VBR and low-latency rate control mode with all supported resolutions(4kp60/4kp30/1080p60) from the command line.
    • Frequency: Always
    • Workaround: None.
NOTE: TRD has been tested with CBR rate control mode and it is working fine. VBR/low_latency rate control mode is disabled in GUI but, enabled in cmd line app for user experience.
  • Image overlapping observed with the SDI pipeline(SDIRx+VCU+SDITx) at 4kp60.
    • Frequency: Always
    • Workaround: run the following command:
Code Block
$ killall -9 modetest
$ source /media/card/
    • No overlapping issue with 4kp30 and 1080p60 pipeline.
  • SDI-Tx link up issue is observed after booting in SDI design.
    • Frequency: Rare
    • Workaround: Re-launch the modetest by running “$ source /media/card/” from the command line.

6.2 Limitations

  • TRD supports 4kp and 1080p resolutions output sink.
  • All VCU parameters are not exposed at GStreamer.
  • This design is validated with HDMI sources (ABOX/Nvidia shield Pro) and DP/HDMI-Tx monitors that are mentioned earlier in the compatibility section. Other sources may or may not work with the TRD out of the box.
  • In HEVC/AVC, max supported bitrate is 60Mbps for a single pipeline.
  • To achieve reliable total aggregate 4kp60 system bandwidth (1x4kp60 Or 2x4kp30 Or 4x1080p60 pipelines) b-frames should be 0, l2-cache should be enabled, gop-mode should be either basic or low_delay_p and aggregate bitrate should be 60Mbps due to bandwidth constraints.
  • TRD is tested only with MONOPRICE 1x4HDMI Splitter which works up to 4kp30.
  • This design is validated with Teranex Mini HDMI to SDI 12G and SDI to HDMI 12G , that are mentioned earlier in the compatibility section.
  • Support for only Single stream playback from the command line is available with SDI Design.
  • In DP for File playback, video file resolution should match to DP's native resolution.

7 Support

To obtain technical support for this reference design, go to the:
  • Xilinx Answers Database to locate answers to known issues
  • Xilinx Community Forums to ask questions or discuss technical details and issues. Please make sure to browse the existing topics first before filing a new topic. If you do file a new topic, make sure it is filed in the sub-forum that best describes your issue or question e.g. Embedded Linux for any Linux related questions. Please include "ZCU106 VCU TRD" and the release version in the topic name along with a brief summary of the issue.