Zynq UltraScale+ MPSoC VCU TRD 2018.2

1 Revision History

This wiki page complements the 2018.2 version of the VCU TRD.

Change Log:

• Updated all projects, IPs, and tools versions to 2018.2
• Frame-drops fixed in 4Kp60 AVC pipeline till 60 Mbps.

---

2 Overview

The Zynq® UltraScale+™ MPSoC Video Codec Unit (VCU) Targeted Reference Design (TRD) consists of an embedded video encoding/decoding application that runs on the Processing System (PS). Overall functionality of the TRD is partitioned between the Processing System (PS), Video Codec Unit, and Programmable Logic (PL) for optimal performance. The below figure shows the TRD block diagram. It consists of four Design Modules (DM1, DM2, DM3, DM4). The components of each design module are highlighted in unique colors in the diagram. The remaining blocks are common to all design modules as shown.



The primary goal of this TRD is to demonstrate the capabilities of the VCU core which is an integrated hard block present in Zynq UltraScale+ MPSoC EV devices. The TRD serves as a platform for the user to tune the performance parameters of VCU and arrives at an optimal configuration for encoder and decoder blocks for their specific use case. The TRD uses Vivado IP Integrator (IPI) flow for building the hardware design and Xilinx Yocto PetaLinux flow for software design. It uses Xilinx IPs and software drivers to demonstrate the capabilities of different components. The TRD consists of four design-modules described in section 4.1.

The TRD supports the following video interfaces:

Sources:

• Test pattern generator (TPG) implemented in the PL.
• HDMI-Rx capture pipeline implemented in the PL.
• MIPI CSI-2 Rx capture pipeline implemented in the PL.
• File source (SD card, USB storage, SATA hard disk).
• SDI-Rx capture pipeline implemented in the PL.

Sinks:

• DP Tx display pipeline in the PS.
• HDMI-Tx display pipeline implemented in the PL.
• SDI-Tx display pipeline implemented in the PL.

This tutorial contains information about:

• How to set up the ZCU106 evaluation board and run the TRD.
• How to build all the TRD components via detailed step-by-step tutorials.

Additional material available for reference:

• Zynq UltraScale+ MPSoC VCU TRD user guide, UG1250: The User Guide (UG) provides the list of features, software architecture, and hardware architecture.

---

3 Software Tools and System Requirements

3.1 Hardware

Required:

• ZCU106 evaluation board (rev B/C/D/E/F/1.0) with power cable
• Monitor with DisplayPort/HDMI input supporting 3840x2160 resolution
• Display Port cable (DP certified)
• HDMI cable
• Class-10 SD card
• GooBang Doo ABOX 2017 player with the resolution set to 4KP30, color space to VUY24 and HDMI cable
• NVIDIA SHIELD Pro
• USB mouse
• Ethernet cable
• SDI Receiver - Black Magic Teranex Mini HDMI to 12G converter
• SDI Transmitter - Black Magic Teranex Mini 12G to HDMI converter

Optional:

• USB pen drive formatted with FAT32 file system and hub
• SATA drive formatted with FAT32 file system, external power supply, and data cable
• LI-IMX274MIPI-FMC image sensor daughter card

3.2 Software

Required:

• Linux host machine for all tool flow tutorials (see UG1144 for detailed OS requirements)
• PetaLinux Tools version 2018.2 (see UG1144 for installation instructions)
• Git distributed version control system
• Silicon Labs quad CP210x USB-to-UART bridge driver
• Serial terminal emulator e.g. teraterm
• Reference Design Zip File
  • ZCU106 rev B/C/D/E/F/1.0: including all source code and project files.

3.3 Download, Installation, and Licensing

The Vivado Design Suite User Guide explains how to download and install the Vivado® Design Suite tools, which includes the Vivado Integrated Design Environment (IDE), High-Level Synthesis tool, and System Generator for DSP. This guide also provides the information about licensing and administering evaluation and full copies of Xilinx design tools and intellectual property (IP) products. The Vivado Design Suite can be downloaded from here.

LogiCORE IP Licensing

The following IP cores require a license to build the design.

• Video Test Pattern Generator (TPG) - Free License but must be downloaded
• Video Timing controller (VTC) - Free License but must be downloaded
• Video Mixer- Purchase license - Free License but must be downloaded
• Video PHY Controller - Included with Vivado
• HDMI-Rx/Tx Subsystem - Purchase license (Hardware evaluation available)
• Video Processing Subsystem (VPSS) - Free License but must be downloaded
• MIPI CSI Controller Subsystems (mipi_csi2_rx_subsystem)- Purchase license (Hardware evaluation available)
• SDI- Rx/Tx Subsystem - Included with Vivado

To obtain the LogiCORE IP license, please visit the respective IP product page and get the license.

• AR# 44029 - Licensing - LogiCORE IP Core licensing questions
• Xilinx Licensing FAQ
• LogiCORE IP Project License Terms

3.4 Compatibility

The reference design has been tested successfully with the following user-supplied components.

DisplayPort Monitor:

HDMI Monitor:

HDMI Input Sources:

• GooBang Doo ABOX 2017 player
• NVIDIA SHIELD Pro

DisplayPort Cable:

• Cable Matters DisplayPort Cable-E342987
• Monster Advanced DisplayPort Cable-E194698
• HDMI 2.0 compatible cable

---

4 Design Files

4.1 Design Modules

The TRD consists of four designs which are highlighted in four colors as shown in the above figure.

• DM1 - PL HDMI Video Capture
• DM2 - PL SDI Video Capture
• DM3 - PL SDI Video Capture and SDI Display
• DM4 - Full-fledged VCU TRD

The following table shows the dependency matrix between different modules. For example: DM4 (row) depends on or builds on top of modules DM1.

4.2 Download the TRD

The TRD has been tested on Rev B, Rev C, Rev D, Rev E, Rev F and Rev 1.0 ZCU106 evaluation boards with Production silicon. The following design files can be downloaded from here.