This page gives an overview of the bare-metal driver support for the Xilinx® LogiCORE™ IP AXI USB soft IP.
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Introduction
The AXI USB device IP is a USB device controller IP. It has no support for OTG mode. This IP can be instantiated on FPGA or Zynq or ZynqMP PL. This page describes the usage of AXI USB device IP standalone driver.
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/usb/
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Directory | Description |
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doc | Provides the API and data structure details |
data | Driver .tcl, .mdd file and .yaml files |
examples | Example applications that show how to use the driver features |
src | Driver source files, make and cmakelists file |
Note: AMD Xilinx embeddedsw build flow has been changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki page Porting embeddedsw components to system device tree (SDT) based flow - Xilinx Wiki - Confluence (atlassian.net).
The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in future.
Driver Implementation
For a full list of features supported by this IP,
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Mass storage profile can be tested by compiling xusb_storage_polled_mode.c,xusb_cp9.c,xusb_cp9.h,xusb_storage.h,xusb_types.h,
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USB 2.0 Peripheral Mode
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Below is the testing procedure of AXI USB standalone example which operates as a mass storage gadget
Download and run the generated USB 2.0 example ELF
Connect board setup to standard host(Windows/Linux)machine USB 2.0 port.
Expected Output
You will get a pop-up window on a Windows machine for formatting the size 256MB. After the format completes, you can copy the file to the USB device.
Example Design Architecture
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