This page gives an overview of the bare-metal driver support for the Xilinx® LogiCORE™ IP AXI USB soft IP.
The AXI USB device IP is a USB device controller IP. It has no support for OTG mode. This IP can be instantiated on FPGA or Zynq or ZynqMP PL. This page describes the usage of AXI USB device IP standalone driver.
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/usb/
The source code for the driver is included with the Vitis Unified Software Platform installation and being available in the Xilinx Github repository.
Driver Name | Path in Vitis | Path in Github |
|---|---|---|
usb | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/usbpsu | https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/usb/ |
Note: To view the sources for a particular release, use the rel-version tag in Github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/usb/
The driver source code is organized into different folders. The table below shows the USB driver source organization.
Directory | Description |
|---|---|
doc | Provides the API and data structure details |
data | Driver .tcl, .mdd file and .yaml files |
examples | Example applications that show how to use the driver features |
src | Driver source files, make and cmakelists file |
Note: AMD Xilinx embeddedsw build flow has been changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki page Porting embeddedsw components to system device tree (SDT) based flow - Xilinx Wiki - Confluence (atlassian.net).
The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in future.
For a full list of features supported by this IP,
Axi-USB: https://www.xilinx.com/products/intellectual-property/axi_usb2_device.html
USB 2.0 HS and FS Device controller.
USB 1.1 legacy FS/LS.
Local DMA Engine.
Support device mode only
Host mode is not supported
OTG mode is not supported
Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.
Links to Examples
Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/usb/examples
Test Name | Example Source | Description |
|---|---|---|
USB Mass-Storage Gadget - Poll Mode | This example does a basic read and writes test from the USB drive in polled mode. |
Mass storage profile can be tested by compiling xusb_storage_polled_mode.c,xusb_cp9.c,xusb_cp9.h,xusb_storage.h,xusb_types.h,
files together
USB 2.0 Peripheral Mode
The below gives the testing procedure of axi-usb device standalone example which operates as a mass storage gadget
Testing procedure
Mass storage profile can be tested by compiling files found in the below link
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/usb/examples
Below is the testing procedure of AXI USB standalone example which operates as a mass storage gadget
Download and run the generated USB 2.0 example ELF
Connect board setup to standard host(Windows/Linux)machine USB 2.0 port.
Expected Output
You will get a pop-up window on a Windows machine for formatting the size 256MB. After the format completes, you can copy the file to the USB device.
AXI-USB specific design. This is the customized image of axi-usb and canfd. AXI Interconnect module connected with ULPI.
The below performance results are observed using CrystalDiskMark tool on windows
2023.2
https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2023.2/doc/ChangeLog#L315
2023.1
None
2022.2
None
2022.1
None
2021.2
None
2021.1
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L2220
2020.2
https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.2/doc/ChangeLog#L715
2020.1
https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.1/doc/ChangeLog#L557
2016.2
https://github.com/Xilinx/embeddedsw/blob/xilinx-v2016.2/doc/ChangeLog#L43
2016.1
https://github.com/Xilinx/embeddedsw/blob/xilinx-v2016.1/doc/ChangeLog#L387