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This page provides all the information related to Design Module 7 - VCU TRD Xilinx low latency(LLP2) PS DDR NV12 HDMI design.

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The below table gives information about the features supported in this design. 

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TRD package contents are placed in the following directory structure. The user needs to copy all the files from the $TRD_HOME/images/vcu_llp2_hdmi_nv12/ to the FAT32 formatted SD card directory.

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The vcu_gst_app is a command-line multi-threaded linux Linux application. The command-line application requires an input configuration file (input.cfg) to be provided in the plain text.

Run below modetest command to set CRTC configurations for 4kp60:

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$ vcu_gst_app /media/card/config/1-4kp60/Stream-out/Single_4kp60_HEVC_25_Mbps.cfg

4kp60 NV12 HEVC ultra-low-latency(LLP2) video stream-in pipeline execution.

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$ gst-launch-1.0 udpsrc port=5004 buffer-size=60000000 caps="application/x-rtp, media=video, clock-rate=90000, payload=96, encoding-name=H265" ! rtpjitterbuffer latency=7 ! rtph265depay ! h265parse ! video/x-h265, alignment=nal ! omxh265dec low-latency=1 internal-entropy-buffers=5 ! video/x-raw\(memory:XLNXLL\) ! queue max-size-bytes=0 ! fpsdisplaysink name=fpssink text-overlay=false 'video-sink=kmssink bus-id=a0070000.v_mix hold-extra-sample=1 show-preroll-frame=false sync=true ' sync=true -v

4kp60 NV12 HEVC ultra-low-latency(LLP2) audio+video stream-in pipeline execution. where , 192.168.25.90 is the server’s IP address.

$ sh /media/card/config/1-4kp60/Stream-in/Single_4kp60_HEVC_Audio_Enabled_25_Mbps.sh

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2.1 Overview

The primary goal of the v4l2 capture control software encoder application is to demonstrate the Xilinx’s Ultra Low-Latency feature using the VCU ctrlsw APIs. This application (v4l2_capture_ctrlsw_enc) is an enhanced version of normal VCU ctrlsw app (ctrlsw_encoder). Normal ctrlsw_encoder application is only capable for of file-based encoding, while this app captures data from the HDMI source and does stream-out using Gstreamer libraries.

The v4l2 capture ctrlsw encoder application has the following features:

• Stream out encoded data captured from the HDMI source using RTP streaming.

• Record encoded data captured from HDMI source to a file.

• Supports various encoding options, can be set by config file as an input to the application, similar as to how config file is used for ctrlsw_encoder.

• Supports various latency modes e.g. Xilinx’s Ultra Low Latency (LLP2) mode via --xlnx-slicelat and Low Latency (LLP1) mode via --slicelat, can be set via command line

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As shown in the above figure, the app performs the below list of operations in case of Xilinx’s Ultra Low Latency (LLP2) mode:

1. Application The application enables syncip and programs address ranges as per input video format and resolution.

2. Application calls VIDIOC_DQBUF and sends empty input buffer to encoder using early dequeue mechanism.

3. Encoder The encoder receives this empty buffer and starts generating the read requestrequests.

4. Start DMA command is issued to v4l2 capture driver and capture starts filling the buffer.

5. SyncIP blocks the encoder until framebuffer-write is done writing data corresponding to the read request made by the encoder.

6. Once the encoder is unblocked, it starts encoding data and generating output slices corresponding to unblocked input read requests.

7. Encoded data is feed to Gstreamer AppSrc, and it passed to UDP sink through the RTP payloader to stream-out the encoded data.

8. Similarly, for consecutive buffers v4l2 programs SyncIP, submits buffer to encoder using VIDIOC_DQBUF and syncip block blocks the encoder until v4l2 has written sufficient data. This way syncip maintains the synchronization between the producer (v4l2) and consumer (encoder).

The below figure shows the v4l2 capture control software encoder application software block diagram:

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• Download AR package for V4l2 Control Software Encoder Application from below AR link:

  • AR#76096: 2020.2 Zynq UltraScale+ MPSoC VCU - How to run live capture encode with a Xilinx low latency use case using the ctrlsw_encoder application

• You can download VCU TRD 2020.2 rdf package - containing VCU TRD bsp BSP and designs from the below link:

  • https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1010303044/Zynq+UltraScale+MPSoC+VCU+TRD+2020.2#4.1-Download-the-TRD

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This tutorial shows how to build the above v4l2 control software encoder application’s AR package to generate Linux and boot image using the PetaLinux build tool. It assume assumes that the $TRD_HOME environment variable is set as given below.

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• Source the Petalinux tool-chain using the below command

$ source <path/to/petalinux-installer>/tool/petalinux-v2020.2-final/settings.sh
$ echo $PETALINUX

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