Versions Compared

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

This page provides all the information related to Design Module 12 - VCU TRD Xilinx low latency(LLP2) PL DDR NV16 HDMI design.

...

Refer below link for Board Setup

1.2 Run Flow

The TRD package is released with the source code, Vivado project, Petalinux BSP, and SD card image that enables the user to run the demonstration. It also includes the binaries necessary to configure and boot the ZCU106 board. Prior to running the steps mentioned in this wiki page, download the TRD package and extract its contents to a directory referred to as ‘TRD_HOME' which is the home directory.

Refer Section 4.1 : Download the TRD of Zynq UltraScale+ MPSoC VCU TRD 2020.1 wiki page to download all TRD contents Link will be added <June-05>.

TRD package contents are placed in the following directory structure. The user needs to copy all the files from the $TRD_HOME/images/vcu_llp2_hdmi_nv16/ to FAT32 formatted SD card directory.

...

Configuration files(input.cfg) for various resolutions are placed in the following directory structure in /media/card.

Code Block
config/
├── 1-4kp60
│   ├── Display
│   └── Stream-out
├── 2-1080p60
│   ├── Display
│   └── Stream-out
├── 2-4kp30
│   ├── Display
│   └── Stream-out
└── 4-1080p60
│   └── Stream-out
└── input.cfg

...

Refer below link for detailed run flow steps:

1.3 Build Flow

Refer below link for detailed build flow steps:

...

2 Other Information

2.1 Known Issues

...

...

Pixel Format

GStreamer Format

Media Bus Format

GStreamer HEVC Profile

GStreamer AVC Profile

Kmssink Plane-id

NV16

NV16

UYVY8_1X16

main-422

high-4:2:2

33 and 34

...