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• pl.dtsi: This is a file where all the memory mapped peripheral logic(PL) IP nodes will be available.
• pcw.dtsi: This is a file where the dynamic properties where the PS peripheral needs.
• system-top.dts: This is a file where it contains the memory information, early console and the boot arguments.
• zynqmp.dtsi: This file contains all the PS peripheral information and also the cpu info.
• zynqmp-clk-ccf.dtsi: This file contains all the clock information for the peripheral IPs.
• pl-partial-<RPRM>.dtsi: This is a file where all the memory mapped IP nodes for dynamic function exchange designs(DFX).
• pl-partial-custom-<RPRM>.dtsi: This is a file where we can customize the dfx ip nodes. This will get generated when CONFIG.partial_overlay_custom_dts is set
  • If user issues %xsct set_property CONFIG.partial_overlay_custom_dts "pl-partial-final.dts" command then pl-partial-<RPRM>.dtsi and pl-partial-custom-<RPRM>.dtsi will get created and included in pl-partial-final<RPRM>.dts
  • user should do his changes in pl-partial-custom-<RPRM>.dtsi. With this user can create pl-partial-<rprm>.dtbo or pl-partial-final<RPRM>.dtbo based on his requirements.
• pl-custom.dtsi: This will get generated only when CONFIG.overlay_custom_dts is set. This flag is useful when user want to customize pl.dtsi nodes with user changes when using overlays.
  • If user issues %xsct set_property CONFIG.overlay_custom_dts "pl-final.dts" command then pl.dtsi and pl-custom.dtsi will get created and included in pl-final.dts
  • user should do his changes in pl-custom.dtsi. With this user can create pl.dtbo or pl-final.dtbo based on his requirements.

Apart from these files, based on the board it will generate one more board.dtsi file under the same output directory dt/.  For example, if board is zcu111-reva then it generates dt/zcu111-reva.dtsi.

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• zynqmp-clk-ccf.dtsi has static clock node configuration, if user wants to change any of the clock information update those in system-user.dtsi.
• DTG doesn't support IP that are packaged in a subsystem(multiple BD's)
• Interrupt port width more than one wont be supported.
• When multicore is enabled for the MAC IPs(if the MAC IPs are more than 1) then there is issue with the label in DTG and it fails. But there wont be an issue if the MAC IP is one and multicore is enabled.
• DTG wont support for generation of private peripheral interrupts(PPI).
• DTG supports the video pipeline generation based on the internal TRD designs as mentioned in the wiki https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/25329832/Zynq+UltraScale+MPSoC+VCU+TRD+2018.3
• DTG doesn't support custom IP, For Multimedia use case If there are any custom IPs connected between the video pipeline IPs DTG wont support those, user may need to add the input and output ports.
• For broadcaster IP the output can connect to multiple output ports and DTG cant know which output port is a valid for the correct pipeline.
• If there are multiple similar video pipelines in the design user need to add the input and output port information in the nodes. The below wiki gives some info about how to add the input and output ports.
  • DTG limitation for multimedia IPs
• DTG doesn't support non memory-mapped IP's.
• With the current DTG implementation not able to populate the ttc timer properties in pcw.dtsi even if the design has ttc ips. In board dtsi file zynq-7000.dtsi/zynqmp.dtsi/versal.dtsi change the ttc timer name to ttctimer then you will see the entries in pcw.dtsi. We will fix this in 2022.2 release.
• when there are multi ethernet ips in the zynqmp design then getting syntax error for the third IP. Closing the clock with ">" resolves the issue in pl.dtsi file
• if the same peripheral connected to both RPU and APU and you want only RPU to access that please disable the status explicitly 'status = "disabled"' as DTG default generates the nodes for all the accessible peripherals.
• If PS ethernet is connected to gmii-to-rgmii Interface User should add 'phy1' node references into either board dtsi file or system-user.dtsi files to not see the below build failures. This cannot be autogenerated as DTG doesn't know the connected board phy info.

           ERROR (phandle_references): /axi/ethernet@ff0c0000/mdio/gmii_to_rgmii_1@8: Reference to non-existent node or label "phy1"

           ERROR: Input tree has errors, aborting (use -f to force output)

           Reference node can be found at https://github.com/Xilinx/device-tree-xlnx/blob/xlnx_rel_v2022.2/device_tree/data/kernel_dtsi/2022.2/BOARD/zcu1275-revb.dtsi#L54-L74

New Features:

• Multi concat block support added
• Added DPU IP support
• Replaced the hardcoded values with the macros for reset and power.
• Added dma channels for axi_mcdma IP support in DTG.
• Generate the memory node for each axi_noc IP for Versal
• Added dfx support in DTG
• generating the aie clock node for versal designs if they have aie ip.
• For aie node you can find the detailed doc in below
• https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/soc/xilinx/xlnx%2Cai-engine.yaml

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xsct % bsp config dt_overlay true

xsct % bsp config partial_overlay_custom_dts "pl-partial-final"

xsct % platform generate

How to enable DT OVERLAY from DTG

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Using HSI commands
1.Clone the device tree repo
https://github.com/Xilinx/device-tree-xlnx
2) Go to the prompt
% hsi
hsi v2017.3 (64-bit)SW Build 2018833 on Wed Oct 4 19:58:07 MDT 2017
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
3)
hsi% open_hw_design system.hdf
4)
hsi% set_repo_path device-tree-xlnx
5)
hsi% create_sw_design -proc psu_cortexa53_0 sd22 -os device_tree
6)
hsi% set_property CONFIG.dt_overlay true [get_os]
7)
hsi% generate_target -dir dt/
hsi% ls dt/
pcw.dtsi pl.dtsi sd22.mss system-top.dts zynqmp-clk-ccf.dtsi zynqmp.dtsi

Using XSCT (From 2019.2 release no hsi support)

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3) hsi open_hw_design system.xsa

4) hsi set_repo_path /home/vabbarap/workspace/sync_dt_tip/dt_15_12_2019 (DTG repo path)

5) hsi create_sw_design -proc psu_cortexa53_0 sd22 -os device_tree 

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