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This page provides all the information related to Design Module 6 - VCU TRD HDMI Video Capture design.

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Resolution

GUI

Command Line

Single Stream

Single Stream

4Kp60

X

4Kp30

X

1080p60

X

√ - Supported
x - Not supported

The below table gives information about the features supported in this design.

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Refer below link for Board Setup

1.2 Run Flow

The TRD package is released with the source code, Vivado project, Petalinux BSP, and SD card image that enables the user to run the demonstration. It also includes the binaries necessary to configure and boot the ZCU106 board. Prior to running the steps mentioned in this wiki page, download the TRD package and extract its contents to a directory referred to as TRD_HOME which is the home directory.

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Refer below link for detailed run flow steps

1.3 Build Flow

Refer below link for Build Flow

Zynq UltraScale+ MPSoC VCU TRD 2020.1 - Build Flow

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2 Other Information

2.1 Known Issues

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Slice:
The number of slices produced for each frame. Each slice contains one or more complete macroblock/CTU row(s). Slices are distributed over the frame as regularly as possible. If slice-size is defined as well more slices may be produced to fit the slice-size requirement.
Options:
4-22 4K 4Kp resolution with HEVC codec
4-32 4K 4Kp resolution with AVC codec
4-32 1080p resolution with HEVC codec
4-32 1080p resolution with AVC codec

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