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The table below lists the available hardware designs and XSA path. These can be found in the prebuilt prebuild folder in the package under "pl/prebuiltprebuild".
| Design | Project | XSA file |
| VCU TRD | VCU TRD | zcu106_trd.xsa |
| Multistream Audio | HDMI-Rx + VCU + HDMI-Tx + Audio and MIPI-Rx + VCU + HDMI-TX + Audio - [ I2S-Rx + I2s-Tx ] | zcu106_audio.xsa |
| 10G Ethernet Video streaming | 10G HDMI-Rx + VCU + HDMI-Tx | zcu106_10g.xsa |
| SDI Capture and Display with Audio | SDI-Rx + VCU + SDI-Tx + Audio + PLDDR | zcu106_plddr_sdi.xsa |
| HDMI Video Capture | HDMI-Rx + VCU | zcu106_hdmirx.xsa |
| HDMI Video Display | VCU + HDMI-Tx | zcu106_hdmitx.xsa |
| SDI Video Capture | SDI-Rx + VCU | zcu106_sdirx.xsa |
| SDI Video Display | VCU + SDI-Tx | zcu106_sditx.xsa |
| PL DDR HDMI Capture and Display | HDMI-Rx + VCU + HDMI-Tx + PL DDR | zcu106_plddr_hdmi.xsa |
| PCIe Encode, Decode and Transcode | PCIe XDMA + VCU | zcu106_pcie.xsa |
Xilinx Low Latency PS DDR NV12 HDMI Capture and Display | HDMI-Rx + VCU + HDMI-Tx + Sync IP | zcu106_llp2_nv12.xsa |
| Xilinx Low Latency PL DDR NV16 HDMI Capture and Display | HDMI-Rx + VCU + HDMI-Tx + PL DDR + Sync IP | zcu106_llp2_nv16.xsa |
| Xilinx Low Latency PL DDR XV20 HDMI Capture and Display | HDMI-Rx + VCU + HDMI-Tx + PL DDR + Sync IP | zcu106_llp2_xv20.xsa |
| Xilinx Low Latency PL DDR XV20 SDI Capture and Display | SDI-Rx + VCU + SDI-Tx + PLDDR + SYNC IP | zcu106_llp2_sdi.xsa |
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| Code Block | ||
|---|---|---|
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% petalinux-config --get-hw-description=$TRD_HOME/pl/prebuild/vcuzcu106_trd |
NOTE:
- If the Vivado project is modified, the user is expected to configure the bsp with the modified .xsa file and build.
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| Code Block | ||
|---|---|---|
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% petalinux-config --get-hw-description=$TRD_HOME/pl/vcuzcu106_trd/ |
- Create a soft link of design dtsi file to system-user.dtsi using below command
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