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Design Module # | Project Name | TRD Pre-built images | Hardware design | Description |
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1 | vcu_multistream_nv12 | zcu106_trd | Multi-stream design supporting HDMI-Rx, TPG, MIPI, HDMI-Tx, DP along with showcasing capabilities of VCU | |
2 | vcu_sdi_xv20 | zcu106_picxo_plddr_sdi_8ch | Design showcasing HLG/Non-HLG Video + 2/8 channels Audio Capture and Display through SDI interface along with the capabilities of VCU with PL DDR supporting 4:2:2 10 bit XV20 format encoding from PS DDR and decoding from PL DDR | |
3 | vcu_audio | zcu106_audio | Design supporting I2S and HDMI Audio with video capture of HDMI-Rx/MIPI-Rx and showcasing capabilities of VCU | |
4 | 10G HDMI Video Capture and Display | This Design Module is discontinued in 2021.2 VCU TRD release. | ||
5 | vcu_pcie | zcu106_pcie | Design to showcase file transfer from HOST(x86) machine over PCIe interface and encode, decode or transcode it on ZCU106 board having VCU connected as PCIe endpoint and write back the encode, decoded or transcoded data to the HOST machine. | |
6 | vcu_plddrv1_hdr10_hdmi | zcu106_HDR10_DCI4K | VCU based HDMI design to showcase encoding with PS DDR and decoding with PL DDR. It supports the reception and insertion of HDR10 static metadata for HDMI and also DCI4K Feature. HDR10 PLDDR_V1 corresponds to old PLDDR part : MT40A256M16GE-075E | |
7 | Xilinx Low Latency PS DDR NV12 HDMI Audio Video Capture and Display | vcu_llp2_hdmi_nv12 | zcu106_llp2_audio_nv12 | VCU based HDMI audio video design to showcase ultra low latency support using Sync IP, encoding and decoding with PS DDR for NV12 format |
8 | Xilinx Low latency PL DDR NV16 HDMI Video Capture and Display | These two design modules are now merged as single design module #12 - Xilinx Low Latency PL DDR HDMI Video Capture and Display. | ||
9 | Xilinx Low latency PL DDR NV20 HDMI Video Capture and Display | |||
10 | Xilinx Low Latency PL DDR XV20 SDI Video Capture and Display | vcu_llp2_sdi_xv20 | zcu106_picxo_llp2_sdi | VCU based SDI design to showcase ultra low latency support using Sync IP, encoding with PS DDR and decoding with PL DDR for XV20 format |
11 | Quad Sensor MIPI CSI Video Capture and HDMI Display | This Design Module is been discontinued since 2021.1 VCU TRD release. | ||
12 | vcu_llp2_plddr_hdmi | zcu106_llp2_xv20_nv16 | VCU based HDMI design to showcase ultra low latency support using Sync IP, encoding with PS DDR and decoding with PL DDR for NV16 and XV20 format |
YUV444 8-bit/10-bit supported TRD is now officially releasedVCU TRD 2021.2 YUV444 beta release is officially available now. To get more information on design and to download the released rdf package, you can refer to Zynq UltraScale+ MPSoC VCU TRD 2021.2 - YUV444 Video Capture and Display
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