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PL330 Standalone Driver

Introduction

This page gives an overview of pl330/dmaps DMA driver which is available as part of the Xilinx Vivado and

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Vitis distribution.

Table of Contents

Table of Contents

How to enable

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For more information, please refer to PL330 DMA controller chapter in Zynq TRM (UG585).

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository. 

Driver Name

Path in Vitis

Path in Github

dmaps

<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/dmaps

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/dmaps


Note: To view the sources for a particular release, use the rel-version tag in github.  For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/

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The driver source code is organized into different folders.

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  The table below shows the dmaps driver source organization

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Directory

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Description

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doc

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Provides the API and data structure details

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data

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Driver .tcl and

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.mdd file

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examples

Example applications that show how to use the driver

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Features Supported

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features

src

Driver source files

Driver Implementation

For a full list of features supported by this IP, please refer to PL330 DMA controller chapter in Zynq TRM (UG585).

Features

Controller/Driver features supported

  • Controller supports only Memory to Memory Transfers

  • Flexible scatter-gather memory transfers

    • Full control over addressing for source and destination

    • Define AXI transaction attributes

    • Manage byte streams

  • Eight cache lines and each cache line is four words wide

  • Eight concurrent DMA channels threads

    • Allows multiple threads to execute in parallel

    • Issue commands for up to eight read and up to eight write AXI transactions

  • Eight interrupts to the PS interrupt controller and the PL

  • Eight events within DMA Engine program code

  • 128 (64-bit) word MFIFO to buffer the data that the controller writes or reads during a transfer

  • Security

    • Dedicated APB slave interface for secure register accessing

    • Entire controller is configured as either secure or non-secure

  • Memory-to-memory DMA transfers

  • Four PL peripheral request interfaces to manage flow control to and from the PL logic

    • Each interface accepts up to four active requests

Standalone Driver Supported Features

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Test cases

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Known Issues and Limitations

  • Peripheral interface is not tested/supported

  • Unaligned transfers are not supported

Example Applications

DMAPS driver supports a basic interrupt examples describing how its different features can be exercised. These example applications can be imported into the Vitis IDE from the Board Support Package  settings tab. 

Links to Examples

Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/dmaps/examples

Test Name

Example Source

Description

DMAPS interrupt example

xdmaps_example_w_intr.c

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Known issues and Limitations

  • Peripheral interface is not tested/supported
  • Unaligned transfers are not supported

Change Log

2020.2

Summary:

Support for parallel makefile execution

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Basic DMAPS interrupt example demonstrating one transfer over first channel.

Example Application Usage

DMAPS Interrupt example

Basic DMAPS interrupt example demonstrating one transfer over first channel.

Expected Output

Test round 0
Successfully ran XDMaPs_Example_W_Intr

Example Design Architecture

NA

Performance

NA

Change Log

2021.1

https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2021.1/doc/ChangeLog#L243

2020.2

https://github.com/Xilinx/embeddedsw/

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blob/

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release-

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2020.2/

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doc/

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ChangeLog#L612

2020.1

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Minor bug fix for channel boundary check.

Commits:

https://github.com/Xilinx/embeddedsw/

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blob/

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release-

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2020.1/

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doc/

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ChangeLog#L33

2019.2

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Summary:

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Commits:

https://github.com/Xilinx/embeddedsw/

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blob/

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release-

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2019.2/

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doc/ChangeLog#L12

2019.1

None

2018.3

None

2018.2

None

2018

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  • None

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  • None

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  • None

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  • None

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1

None

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  • None

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  • None

Related Links

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