This page gives an overview of pl330/dmaps DMA driver which is available as part of the Xilinx Vivado and Vitis distribution.
For more information, please refer to PL330 DMA controller chapter in Zynq TRM (UG585).
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
Driver Name | Path in Vitis | Path in Github |
|---|---|---|
dmaps | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/dmaps | https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/dmaps |
Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx_v2021.1/XilinxProcessorIPLib/drivers/dmaps |
The driver source code is organized into different folders. The table below shows the dmaps driver source organization.
Directory | Description |
|---|---|
doc | Provides the API and data structure details |
data | Driver .tcl and .mdd file |
examples | Example applications that show how to use the driver features |
src | Driver source files |
For a full list of features supported by this IP, please refer to PL330 DMA controller chapter in Zynq TRM (UG585).
Controller supports only Memory to Memory Transfers
Flexible scatter-gather memory transfers
Full control over addressing for source and destination
Define AXI transaction attributes
Manage byte streams
Eight cache lines and each cache line is four words wide
Eight concurrent DMA channels threads
Allows multiple threads to execute in parallel
Issue commands for up to eight read and up to eight write AXI transactions
Eight interrupts to the PS interrupt controller and the PL
Eight events within DMA Engine program code
128 (64-bit) word MFIFO to buffer the data that the controller writes or reads during a transfer
Security
Dedicated APB slave interface for secure register accessing
Entire controller is configured as either secure or non-secure
Memory-to-memory DMA transfers
Four PL peripheral request interfaces to manage flow control to and from the PL logic
Each interface accepts up to four active requests
Peripheral interface is not tested/supported
Unaligned transfers are not supported
DMAPS driver supports a basic interrupt examples describing how its different features can be exercised. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.
Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/dmaps/examples
Test Name | Example Source | Description |
|---|---|---|
DMAPS interrupt example | Basic DMAPS interrupt example demonstrating one transfer over first channel. |
Basic DMAPS interrupt example demonstrating one transfer over first channel.
Expected Output
|
NA
NA
2021.1
https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2021.1/doc/ChangeLog#L243
2020.2
https://github.com/Xilinx/embeddedsw/blob/release-2020.2/doc/ChangeLog#L612
2020.1
https://github.com/Xilinx/embeddedsw/blob/release-2020.1/doc/ChangeLog#L33
2019.2
https://github.com/Xilinx/embeddedsw/blob/release-2019.2/doc/ChangeLog#L12
2019.1
None
2018.3
None
2018.2
None
2018.1
None