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Refer below link for Board Setup

  • Zynq UltraScale+ MPSoC VCU TRD 2020.2 Board Setup (TODO: Update link once 2020.2 wiki pages are published)

  • I2S Audio. signals from MPSoC PL fabric are connected to PMOD0 GPIO Header (J55 - right angle female connector )

  • PMOD I2S2 Add on card connects to J55 connector and its Master/Slave select jumper (JP1) should be placed into the Slave (SLV) position

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Refer below link to download all TRD contents.

  • Refer Section 4.1 : Download the TRD of Zynq UltraScale+ MPSoC VCU TRD 2020.2 wiki page to download all TRD contents. (TODO: Update Section 4.1 link, once 2020.2 wiki pages are published)

TRD package contents are placed in the following directory structure. The user needs to copy all the files from the $TRD_HOME/images/vcu_audio/ to FAT32 formatted SD card directory.

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Refer below link for detailed run flow steps

1.3 Build Flow

Refer below link for Build Flow

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2 Other Information

2.1 Known Issues

2.2 Limitations

  • For playback in DP, video input resolution should match to DP's native resolution. This constraint is due to the support of the GUI. In the GUI case if we allow video source other than native resolution(by setting full screen overlay) then the graphics layer will disappear. To recover back GUI user need to kill and relaunch the GUI app. To avoid such condition TRD only supports video input resolution which is equal to DP's native resolution.

  • For Petalinux related limitations please refer: PetaLinux 2020.2 - Product Update Release Notes and Known Issues (TODO: Verify once 2020.2 is released)

  • For VCU related limitations please refer AR# 66763: LogiCORE H.264/H.265 Video Codec Unit (VCU) - Release Notes and Known Issues, Xilinx Zynq UltraScale+ MPSoC Video Codec Unit and PG252 (TODO: Verify all links once 2020.2 is released)

2.3 Optimum VCU Encoder parameters for use-cases:

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