Zynq UltraScale+ MPSoC VCU HDMI ROI TRD 2020.1

This page provides all the information related to VCU HDMI ROI TRD design.

Table of Contents

1 Overview

The primary goal of this VCU ROI design is to demonstrate the use of DPU (Deep learning Processor Unit) block for extracting the ROI (Region of Interest) from input video frames and to use this information to perform ROI based encoding using VCU (Video Codec Unit) encoder hard block present in Zynq UltraScale+ EV devices.

The design will serve as a platform to accelerate Deep Neural Network inference algorithms using DPU and demonstrate the ROI feature of VCU encoder. The design uses a Deep Convolutional Neural Network (CNN) named Densebox, running on DPU to extract ROI Information (e.g. ‘face’ in this case).
The Design will use Vivado IPI flow for building the hardware platform and Xilinx Yocto Petalinux flow for software design. It will use Xilinx IP and Software driver to demonstrate the capabilities of different components.

The Vitis platform will be created from the Vivado/PetaLInux build artifacts, and then using the Vitis acceleration flow will be used to insert the DPU into the platform to create the final bitstream.

The following figure shows one of the use cases (Serial pipeline) with face detection with enhanced ROI on ZCU106.

Serial: Face detection with enhanced ROI on ZCU106.

The following figure shows one of the use cases (streaming pipeline) with face detection with enhanced ROI on ZCU106.

Streaming: Face detection with enhanced ROI on ZCU106.

1.1 System Architecture

The following figure shows the block diagram of the ROI design

1.2 Hardware Architecture

This section gives a detailed description of the blocks used in the hardware design. The functional block diagram of the design is shown in the below figure.

There are seven primary Sections in the design.

  • HDMI Capture Pipeline:

    • Captures video frame buffers from Capture source in 4K Resolution, NV12 Format

    •  Writes the buffers into DDR Memory with Frame Buffer Write IP

  • Multi-scaler Block:

    • Reads the Video Buffers from DDR Memory

    • Scales down the buffer to the 640x360 size (suitable for dpu)

    • Converts the format from NV12 to BGR

    • Writes the Down-scaled buffer to DDR Memory

  • DPU Block: 

    • Reads the downscaled buffers from DDR Memory

    • Runs the Densebox algorithm to generate the ROI information for each frame buffer

    • Passes the ROI information to VCU Encoder

  • VCU Encoder: 

    • Reads the 4K NV12 Buffer from DDR Memory

    • Receives the ROI metadata from DPU IP

    • Encodes the video buffers based on the ROI Information

    • Finally writes the encoded stream to DDR Memory

  • PS GEM:

    • Reads the Encoder stream from DDR Memory

    • Streams out the encoded stream via Ethernet

  • VCU Decoder:

    • Decodes the received encoded frame and writes to memory

  • HDMI-Tx:

    • Displays the decoded frames on HDMI Display

This design supports the following video interfaces:


  • HDMI-Rx capture pipeline implemented in the PL

  • File source (SD card, USB storage, SATA hard disk)

  • Stream-In from network or internet


  • HDMI-Tx display pipeline implemented in the PL

  • Stream-out on network or internet

VCU Codec

  • Video Encoder/Decoder capability using VCU hard block in PL 

  • H.264/H.265 encoding

  • Encoder/decoder parameter configuration using OMX interface



Streaming Interfaces

1G Ethernet PS GEM

Video Format


Supported Resolution


1.3 VCU ROI Software

1.3.1 GStreamer Pipeline

The GStreamer plugin demonstrates the DPU capabilities with Xilinx VCU encoder’s ROI(Region of Interest) feature. The plugin will detect ROI (i.e. face co-ordinates) from input frames using DPU IP and pass the detected ROI information to the Xilinx VCU encoder. The following figure shows the data flow for GStreamer pipeline of stream-out use case.

Block Diagram of Stream-out Pipeline

fd = v4l2 frame data, fd' = DPU compatible frame data

As shown in the above figure, the stream-out GStreamer pipeline performs the below list of operations:

  1. v4l2src captures the data from HDMI-Rx in NV12 format and pass to xlnxroivideo1detect GStreamer plugin

  2. xlnxroivideo1detect GStreamer plugin will scale down to 640x360 resolution and convert the data into BGR format

  3. 640x360 BGR frame will be provided to DPU IP as an input to find ROI (i.e. face co-ordinates)

  4. Extracted ROI information will be passed to VCU encoder

  5. The encoder will encode the input data by encoding ROI regions with high quality as compared to non-ROI region using received ROI information

  6. Stream-out the encoded data using RTP protocol

The following figure shows the data flow for the GStreamer pipeline of stream-in use cases.

Block Diagram of Stream-in Pipeline

fd = Gst-Omx Frame data

As shown in the above figure, the stream-in GStreamer pipeline performs the below list of operations:

  1. Stream-in the encoded data using RTP protocol

  2. The Xilinx VCU decoder will decode the data

  3. Display the decoded data on HDMI-Tx display

The below figure shows the xlnxroivideo1detect GStreamer plugin data flow.

As shown in the above figure, our xlnxroivideo1detect GStreamer plugin will perform below the list of operations:

  1. DPU is initialized

  2. DPU GStreamer plugin receives the data frame from HDMI-Rx through a v4l2src plugin

  3. Create the DPU task

  4. Scale the input frame to 640x360 resolution using Xilinx Scaler IP

  5. Convert the input frame data format from NV12 to BGR format using Xilinx Color Space Converter(CSC) soft IP

  6. Prepare the OpenCV image using BGR data

  7. Pass the intermediate OpenCV image to the DPU

  8. Run the DPU task

  9. Extract the ROI(face) co-ordinates from the DPU output

  10. Map the detected face co-ordinates to the original input frame resolution

  11. Fill the ROI metadata buffer using extracted ROI (face) co-ordinates

  12. Pass the ROI metadata buffer and input NV12 frame data buffer to the Xilinx VCU encoder

  13. De-initialize the DPU task

1.3.2 DPU(Deep Learning Processor Unit)

DPU is a programmable engine optimized for deep neural networks. It is a group of parameterizable IP cores pre-implemented on the hardware with no place and route required. The DPU is released with the Vitis AI specialized instruction set, allowing efficient implementation of many deep learning networks.

Refer to DPU IP PG338 and UG1354 to know more details on DPU.

The following figure shows the DPU Top-Level Block Diagram.

DPU Top-level Block Diagram

The DPU IP can be implemented in the programmable logic (PL) of the selected Zynq® UltraScale+™ MPSoC device with direct connections to the processing system (PS). The DPU requires instructions to implement a neural network and accessible memory locations for input images as well as temporary and output data. A program running on the application processing unit (APU) is also required to service interrupts and coordinate data transfers.

The following figure shows the sequence of operations performed on the DPU device.

The following sequence of steps are performed to access and run face detection using the DPU device:

  1. DPU device is initialized

  2. Instantiate a DPU Task from DPU Kernel and allocate corresponding DPU memory buffer

  3. Set the input image to created DPU task

  4. Run the DPU task to find the faces from the input image

  5. DPU device is uninitialized

1.4 Software Tools and System Requirements



  • ZCU106 evaluation board (rev C/D/E/F/1.0) with power cable

  • Monitor with HDMI input supporting 3840x2160 resolution or 1920x1080 resolution

  • HDMI cable 2.0 certified

  • Class-10 SD card

  • Ethernet cable


  • USB pen drive formatted with the FAT32 file system and hub

  • SATA drive formatted with the FAT32 file system, external power supply, and data cable

Software Tools


Download, Installation, and Licensing of Vivado Design Suite 2020.1

The Vivado Design Suite User Guide explains how to download and install the Vivado® Design Suite tools, which include the Vivado Integrated Design Environment (IDE), High-Level Synthesis tool, and System Generator for DSP. This guide also provides information about licensing and administering evaluation and full copies of Xilinx design tools and intellectual property (IP) products. The Vivado Design Suite can be downloaded from here.

LogiCORE IP Licensing

The following IP cores require a license to build the design.

  • Video Mixer- Included with Vivado - PG243

  • Video PHY Controller - Included with Vivado - PG203

  • HDMI-Rx/Tx Subsystem - Purchase license (Hardware evaluation available) - PG235 & PG236

  • Video Processing Subsystem (VPSS) - Included with Vivado - PG231

To obtain the LogiCORE IP license, please visit the respective IP product page and get the license.


The reference design has been tested successfully with the following user-supplied components.

HDMI Monitor:





LG 27UD88

3840 x 2160 @ 30Hz

Samsung LU28ES90DS/XL

3840 x 2160 @ 30Hz


  • HDMI 2.0 compatible cable

 The below table provides the performance information:


FPS Achieved


FPS Achieved


26 - 30



Above FPS are measured withgop-mode=basic gop-length=60 b-frames=0 target-bitrate=1500 num-slices=8 control-rate=constant prefetch-buffer=true low-bandwidth=false qp-mode=roi encoder parameters for AVC and HEVC.

1.5 Board Setup

The below section will provide the information on the ZCU106 board setup for running ROI design.

  1. Connect the Micro USB cable into the ZCU106 Board Micro USB port J83, and the other end into an open USB port on the host PC. This cable is used for UART over USB communication.

  2. Insert the SD card with the images copied into the SD card slot J100. Please find here how to prepare the SD card for a specific design.

  3. Set the SW6 switches as shown in the below Figure. This configures the boot settings to boot from SD.

  4. Connect 12V Power to the ZCU106 6-Pin Molex connector

  5. Connect one end of HDMI cable to the board’s P7 stacked HDMI connector (lower port) and another end to HDMI source

  6. Connect one end of HDMI cable to the board’s P7 stacked HDMI connector (upper port) and another end to the HDMI monitor

  7. For a USB storage device, connect the USB hub along with the mouse. (Optional)

  8. For SATA storage device, connect SATA data cable to SATA 3.0 port. (Optional)

  9. Set up a terminal session between a PC COM port and the serial port on the evaluation board (See the Determine which COM to use to access the USB serial port on the ZCU106 board for more details).

  10. Copy the VCU-HDMI-ROI images into the SD card and insert the SD card on the board

  11. The below images will show how to connect interfaces on the ZCU106 board

1.6 Run Flow

The VCU ROI TRD package is released with the source code, Vivado project, Petalinux BSP, and SD card image that enables the user to run the demonstration. It also includes the binaries necessary to configure and boot the ZCU106 board. Prior to running the steps mentioned in this wiki page, download the VCU ROI TRD package and extract its contents to a directory referred to as TRD_HOME which is the home directory.

Refer below link to download the VCU HDMI ROI TRD package.

TRD package contents are placed in the following directory structure.

rdf0428-zcu106-vcu-hdmi-roi-2020-1 ├── apu │   └── vcu_petalinux_bsp │   └── xilinx-vcu-roi-zcu106-v2020.1-final.bsp ├── dpu │   └── 0001-Added-ZCU106-configuration-to-support-DPU-in-ZCU106.patch ├── image │   ├── boot │   │   ├── autostart.sh │   │   ├── bd.hwh │   │   ├── bin │   │   ├── BOOT.BIN │   │   ├── boot.scr │   │   ├── config │   │   ├── dpu.xclbin │   │   ├── Image │   │   ├── setup.sh │   │   ├── system.dtb │   │   ├── vcu │   │   └── vitis │   ├── root │   │ └── rootfs.ext4 │ └── sd_card.img ├── pl │   ├── constrs │   │   └── vcu_roi.xdc │   ├── designs │   │   └── zcu106_ROI_HDMI │   ├── prebuild │   │   └── zcu106_ROI_HDMI_wrapper.xsa │   ├── README.md │   └── srcs │   ├── hdl │   └── ip └── README.txt

The below snippet shows the directory structure of various configuration files which are useful for vcu_gst_app to run Display, and Streaming use cases. All these configurations files are placed in the $TRD_HOME/image/boot/config directory.

└── config    ├── 1080p30    │   ├── Display    │   ├── Stream-in    │   └── Stream-out    ├── 4kp30    │   ├── Display    │   ├── Stream-in    │   └── Stream-out    └── input.cfg

1.6.1 Preparing the SD card

There are three ways to prepare the SD card for booting. Each method is detailed below. 

Using ready to test image

Using Pre-built images

  • To Create SD Card with two partitions: Boot(FAT32+Bootable) and Root(EXT4) Refer this Link.

  • Copy boot content fromrdf0428-zcu106-vcu-hdmi-roi-2020-1/image/boot to Boot partition in SD Card

  • Extract rootfs.ext4 from rdf0428-zcu106-vcu-hdmi-roi-2020-1/image/rootto Root partition in SD Card using

  • Boot the board with Flashed SD Card

Use the Output of the Build Flow

  • To Create SD Card with two partitions: Boot(FAT32+Bootable) and Root(EXT4) Refer this Link.

  • For Build Flow refer this steps and copy mentioned generated dpu build images bd.hwh BOOT.BIN boot.scr dpu.xclbin Image system.dtb into BOOT partition of the SD card and extract generated rootfs.ext4 into ROOT partition of SD Card

  • Copy the mentioned boot content config, vitis, autostart.sh, setup.sh from rdf0428-zcu106-vcu-hdmi-roi-2020-1/image/boot/ directory to Boot partition in SD Card

  • Boot the board with Flashed SD Card

1.6.2 Using GStreamer Application (vcu_gst_app)

The vcu_gst_app is a command-line multi-threaded Linux application. The command-line application requires an input configuration file (input.cfg) to be provided in the plain text.

After the board gets booted, the display screen turns to the blue screen; which means it is ready to test. Otherwise before the execution of vcu_gst_app, manually run modetest command to set CRTC configurations.

$ modetest -D a00c0000.v_mix -s 39:3840x2160-30@AR24 &

Display: Capture → (ROI) → Encode → Decode → Display

  • 4Kp30 HEVC Display Pipeline execution using vcu_gst_app

Stream-out: ( Server )

  • Set IP address for server:

  • 4Kp30 HEVC Stream-out Pipeline execution using vcu_gst_app

Stream-in: ( Client )

  • Set IP address for the client:

  • 4Kp30 HEVC Stream-in Pipeline execution using vcu_gst_app

1.7 Build Flow

Refer below link to download the VCU HDMI ROI TRD package.

Unzip the released package.

The following tutorials assume that the $TRD_HOME environment variable is set as given below.

1.7.1 Hardware Build Flow

This section explains the steps to build the hardware platform and generate XSA using the Vivado tool.

Refer to the Vivado Design Suite User Guide: Using the Vivado IDE, UG893, for setting up the Vivado environment.

Refer to the vivado-release-notes-install-license(UG973) for installation.

Make sure that the necessary IP licenses are in place

On Linux:

  • Open a Linux terminal

  • Change directory to $TRD_HOME/pl folder

  • Source Vivado settings.sh

  • Run the following command to create the Vivado IPI project and invoke the GUI and generate XSA required for the platform

  • The project.tcl script does the following

    • Creates project

    • Creates IPI Block design with platform interfaces

    • Runs Synthesis and Implementation

    • Builds bitstream with no accelerators

    • Export the HW to XSA

  • zcu106_ROI_HDMI_wrapper.xsa is created

  • stored in the directory ../zcu106_ROI_HDMI.xsa/

  • at location $TRD_HOME/pl/build/zcu106_ROI_HDMI/zcu106_ROI_HDMI.xsa/

  • This XSA is used by Petalinux for platform creation and also by the Vitis Tool for DPU Kernel Integration.

After executing the script, the Vivado IPI block design comes up as shown in the below figure. Platform Interfaces

The screenshots below show the platform interfaces that have been made available to the Vitis tool for linking in acceleration IP.

In the case of this reference design, the DPU Kernel will be inserted.

After the DPU Kernel is integrated dynamically with the platform using Vitis Flow, the connections are as shown below

  • The DPU Data ports are connected to the HP0 Port(S_AXI_HP0_FPD) of PS .

  • The DPU Instruction port is connected to the S_AXI_LPD port of PS through axi_interconnect_lpd

  • The DPU S_AXI_Control port is connected to the M_AXI_HPM0_LPD port of PS through interconnect_axilite

  • The DPU interrupt is connected to the axi interrupt controller dynamically

1.7.2 Petalinux build Flow

This tutorial shows how to build the Linux image and boot image using the PetaLinux build tool.

PetaLinux Installation: Refer to the PetaLinux Tools Documentation (UG1144) for installation.

  • Source Petalinux settings.sh

  • Create PetaLinux project

  • Configure the PetaLinux project

    • For e.g.

    • using the prebuild XSA

    • using the XSA generated by running the Hardware project.tcl scripts

  • Build the PetaLinux project

1.7.3 Prepare Build Artifacts for Platform Creation

To prepare artifacts required for ZCU106 Vitis platform creation, follow below steps after petalinux build

  • Go to the petalinux build image directory

  • Create linux.bif file as below in images/linux directory. linux.bif file is required to create ZCU106 Vitis platform which has information related to boot components. After zcu106 vitis platform creation this linux.bif file will be part of platform, which is required to build DPU and generate final BOOT.bin

  • Copy generated images into boot and image directory by following below commands. Use created linux.bif to copy into boot directory.

1.7.4 ZCU106 Platform Creation

This section shows how to create a Vitis acceleration platform for the zcu106 using the Vitis IDE.

Choose project workspace and click on Launch to begin

Launch the New Platform Project dialog box using following step:
Go to File > New > Platform Project

Provide a project name “zcu106_dpu“ in the Platform project name field and click Next as shown in below figure

In the Platform Project dialog box, choose Create a new platform from hardware specification (XSA) and provide the XSA path

  • For prebuild XSA use $TRD_HOME/pl/prebuild/ path

  • For generated XSA using vivado build use $TRD_HOME/pl/build/zcu106_ROI_HDMI/zcu106_ROI_HDMI.xsa/ path

Use below setting under Software Specification

  1. Select linux as the operating system, psu_cortexa53 as processor, and 64-bit architecture to create the platform

  2. Uncheck the box for Generate boot components

  3. Click Finish to create your platform project

Go to zcu106_dpu > linux on psu_cortexa53 and add path of required files in Domain: linux_domain

Give the bif file, boot directory, image path, and rootfs path as shown in below figure

  • Use <Path to Petalinux Project>/xilinx-vcu-roi-zcu106-v2020.1-final/images/linux/boot/linux.bif for Bif File

  • Use <Path to Petalinux Project>/xilinx-vcu-roi-zcu106-v2020.1-final/images/linux/boot/ for Boot Components Directory

  • Use <Path to Petalinux Project>/xilinx-vcu-roi-zcu106-v2020.1-final/images/linux/image for Linux Image Directory

  • Use <Path to Petalinux Project>/xilinx-vcu-roi-zcu106-v2020.1-final/images/linux/image/rootfs.ext4 for Linux Rootfs

Right click on the zcu106_dpu project in the Explorer tab and click on Build Project to generate the platform as shown in below figure
The Console tab shows the status of the platform generation.

As shown in below image, zcu106_dpu.xpfm is created under zcu106_dpu > export > zcu106_dpu > zcu106_dpu.xpfm

1.7.5 DPU Build

  • Clone the Vitis-AI repository and apply patch to add support of ZCU106 in Vitis DPU TRD.

The following tutorials assume that the $DPU_TRD_HOME environment variable is set as given below.

The following tutorials assume that the Vitis and XRT environment variable is set as given below.

  • Open a Linux terminal. Set the Linux as Bash mode.

  • The default setting of DPU is B4096 with RAM_USAGE_LOW, CHANNEL_AUGMENTATION_ENABLE, DWCV_ENABLE, POOL_AVG_ENABLE, RELU_LEAKYRELU_RELU6, Softmax. Read the $DPU_TRD_HOME/prj/Vitis/dpu_conf.vh file to get the details of DPU. You can get all the configurations form PG338. Modify the $DPU_TRD_HOME/prj/Vitis/dpu_conf.vh file can change the default settings.

    • Enable the URAM for ZCU106 DPU Build, The DPU will replace the bram to the uram.

    • Change 'define URAM_DISABLE to `define URAM_ENABLE

  • Build the hardware design

  • Generated SD card files are in $DPU_TRD_HOME/prj/Vitis/binary_container_1/sd_card(SD card Format)

  • Copy generated dpu build images from $DPU_TRD_HOME directory to $TRD_HOME directory

2 Other Information

2.1 Known Issues

2.2 Limitations

2.3 Optimum VCU Encoder parameters for use-cases

Video streaming:

  • Video streaming use-case requires a very stable bitrate graph for all pictures

  • It is good to avoid periodic large Intra pictures during the encoding session

  • Good to avoid periodic Intra frames instead use low-delay-p (IPPPPP…)

  • VBR is not a preferred mode of streaming

Performance: AVC Encoder settings:

  • It is preferred to use 8 or higher slices for better AVC encoder performance

  • AVC standard does not support Tile mode processing which results in the processing of MB rows sequentially for entropy coding

Quality: Low bitrate AVC encoding:

  • The high profile enables 8x8 transform which results in better video quality at low bitrates

3 Appendix A - Input Configuration File (input.cfg)

The example configuration files are stored at /media/card/config/ folder.

Common Configuration:
It is the starting point of a common configuration.

Num of Input:
Provide the number of inputs. It will be 1 only due to single-stream support
Options: 1

Select the video interface.
Options: HDMI

Out Type:
Options: display and stream

Display Rate:
Pipeline frame rate.
Options: 30 FPS

It indicates to the application that the configuration is over.

Input Configuration:
It is the starting point of the input configuration.

Input Num:
Due to single stream support, there will be 1 input configuration only
Options: 1

Input Type:
Input source type.
Options: HDMI, Stream

Network URL. Applicable for stream-in pipeline only.
Options: udp:// (for Network streaming, here is IP address and 5004 is port no)

To tell the pipeline is processed. Pass-through is not supported.
Options: False

The width of the live source.
Options: 3840, 1920

The height of the live source.
Options: 2160, 1080

Enable Roi:
Enable or Disable ROI in the pipeline.
Options: True, False

Relative QP:
The difference of QP value than a neighboring pixel for the ROI region to change the quality of the ROI region.
Option: 32 to -31 (poor to best)

It indicates to the application that the configuration is over.

Encoder Configuration:
It is the starting point of encoder configuration.

Encoder Num:
Due to single-stream support, there will be 1 encoder configuration only
Options: 1

Encoder Name:
Name of the encoder.
Options: AVC, HEVC

Name of the profile.
Options: baseline, main, or high for AVC. Main for HEVC

Rate Control:
Rate control options.
Options: CBR, low-latency

Filler Data:
Options: True, False

QP control mode used by the VCU encoder.
Options: Uniform, Auto, Roi

L2 Cache:
Enable or Disable L2Cache buffer in the encoding process.
Options: True, False

Latency Mode:
Encoder latency mode.
Options: Normal, sub_frame

Low Bandwidth:
If enabled, decrease the vertical search range used for P-frame motion estimation to reduce the bandwidth.
Options: True, False

Gop Mode:
Group of Pictures mode.
Options: Basic, low_delay_p

Target bitrate in Kbps
Options: 1000-1500

B Frames:
Number of B-frames between two consecutive P-frames
Options: 0

The number of slices produced for each frame. Each slice contains one or more complete macroblock/CTU row(s). Slices are distributed over the frame as regularly as possible. If slice-size is defined as well more slices may be produced to fit the slice-size requirement.

4-22 4Kp resolution with HEVC codec
4-32 4Kp resolution with AVC codec
4-32 1080p resolution with HEVC codec
4-32 1080p resolution with AVC codec

GoP Length:
The distance between two consecutive I frames
Options: 1-1000

The format of input data.
Options: NV12

Options: custom

It indicates to the application that the configuration is over.

Streaming Configuration:
It is the starting point of streaming configuration.

Streaming Num:
Due to single-stream support, there will be 1 streaming configuration only
Options: 1

Host IP:
The host to send the packets to
Options: or Windows PC IP

The port to send the packets to
Options: 5004

It indicates to the application that the configuration is over.

Trace Configuration:
It is the starting point of trace configuration.

FPS Info:
To display fps info on the console
Options: True, False

APM Info:
To display the APM counter number on the console
Options: True, False

Pipeline Info:
To display pipeline info on the console
Options: True, False

Loop Playback:
To play display pipeline in the loop
Options: True, False

Loop Interval:
To repeat the playback of the display pipeline after a specific time duration. The default is False.
Options: 5 - 10 sec

It indicates to the application that the configuration is over.

4 Appendix B - HDMI-Rx/Tx Link-up and GStreamer Commands

This section covers configuration of HDMI-Rx using media-ctl utility and HDMI-Tx using modetest utility, along with demonstrating HDMI-Rx/Tx link-up issues and steps to switch HDMI-Rx resolution. It also contains sample GStreamer HDMI Video pipelines for Display, Stream-in and Stream-out ROI use-cases.

  • HDMI source can be locked to any resolution. Run the below command for all media nodes to print media device topology. In the topology log, look for the v_hdmi_rx_ss string to identify the HDMI input source media node.

  • To check the link status, resolution and video node of the HDMI input source, run below media-ctl command.

When HDMI source is connected to 4Kp30 resolution, it shows:

When the HDMI source is not connected, it shows:

Notes for gst-launch-1.0 commands:

Video node for HDMI-Rx source can be checked using media-ctl command. Run below media-ctl command to check video node for HDMI-Rx.

Make sure the HDMI-Rx media pipeline is configured for 4Kp30 resolution and source/sink has the same color format. Run below media-ctl commands to set the resolution and format of the HDMI scaler node.

When HDMI Input Source is NVIDIA SHIELD

Follow the below steps to switch the HDMI-Rx resolution from 1080p30 to 4Kp30.

  • Check current HDMI Input Source Resolution (1080p30) by following the above-mentioned steps

  • Set below configurations in /media/card/input.cfg file for HDMI-1080p30

  • Run vcu_gst_app for current HDMI resolution (1080p30) by executing the following command

  • Change Resolution of HDMI Input Source from 1080p30 to 4Kp30 by following the below steps.

    • Set the HDMI source resolution to 4Kp30 (Homepage → settings → display & sound → Advanced settings → HDMI settings → HDMI display modes → change to 4Kp30)

    • Save the configuration to take place the change

  • Verify the desired HDMI Input Source Resolution (4Kp30) by following the above-mentioned steps

If HDMI-Tx link-up issue is observed after Linux booting, use the following command:

  • For 4K Resolution:

  • For 1080p Resolution:

GStreamer Static Pipelines:

Display: Capture → (ROI) → Encode → Decode → Display

  • Run the following gst-launch-1.0 command to display processed pipeline (capture → roi_plugin → encode → decode → display) on HDMI-Tx

Stream-out: ( Server )

  • Set IP address for server:

  • Run the following gst-launch-1.0 command for stream-out pipeline

Stream-in: ( Client )

  • Set IP address for the client:

  • Run the following gst-launch-1.0 command to display stream-in on HDMI-Tx video using the GStreamer pipeline where 5004 is port number


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