This page shows how to detect an error in a master AXI4 interface using the Verification IP (VIP). It is using the project from this wiki page
Table of Contents
Step 1 : Open the project in Vivado 2017.1
Unzip the wiki_VIP_2.zip file and open the project in Vivado 2017.1.
Step 2 : Configure the IP to testDouble-click on myAXI4IP_0 to open the GUI to configure it. Change the “Target Slave Base Address” to 0x00000FC8.
= Then validate the design and re-generate the BD output products.
Step 3 : Run the simulation
Run the behavioral simulation. We can see in the waveform window that there is communications between myAXI4IP_0 and the VIP.
However this does not mean that the master AXI4 is compliant with the AXI4 specification. If we look at the TCL console and search for the word “ERROR” we can see that the VIP is sending an error related to the AXI4 interface:The error in our case is:
To understand this issue we can look at the section A3.4.1. (as mentioned in error message) in the AMBA® AXI™ and ACE™ Protocol Specification available from ARM website (link)
In the specification we can see the following sentence:
“A burst must not cross a 4KB address boundary
The reason why we can see the error is because myAXI4IP is sending a write burst of 16 32-bit words starting at address 0x00000FC8. This means that the write burst will end at address 0x00001004. This is an error because it cross a 4k boundary which is the address 0x00001000 (4K = 4*1024 = 4096 = 0x1000).Note: The 4K boundary prevents a burst from crossing a boundary between two slaves (the minimum address space allocated to a slave is 4Kbytes)