Finally, create a new guest using ‘xl create -c configfile'.
If your domU is Linux, make sure to add console=ttyPS1,115200 to its kernel command line. In case of dom0less DomUs, you have to edit the boot.source script to add the command line option, then recreate boot.scr with mkimage.
PCI Passthrough assignment
Turn xen.dtb into xen.dts:
dtc -I dtb -O dts xen.dtb > xen.dts
The, edit xen.dts by adding xen,passthrough; under the node of the device to assign, in this case pcie@fd0e0000:
Since the PCIe is a DMA-capable device, it should be included in the SMMU section of the xen.dts. Make sure that the PCIe base address in the IOMMU address map exists in the list of mmu-masters. Please refer the latest version of Zynq Ultrascale + MPSoC TRM (UG1085): a) Find PCIe master device in the table given in the section AXI Master IDs and pick the corresponding master ID, which is 0011010000. b) Expand these 10 bits to 12 bits, the top 2 bits are simply indicating which TBUn device is behind, this can be found in the Zynq UltraScale+ MPSoC TRM Interconnect Functional Description section. For PCIe it is TBU1, i.e. the address will be 010011010000=0x4d0.
Add xen,passthrough and iommus cells in xen.dts. Convert xen.dts back into xen.dtb.
Creation of passthrough-pci.dts: Please see attached passthrough-pci.dts for example of partial device tree file and convert the above dtc into dtb using dtc compiler:
The options needed for pass-through mode are defined below: dtdev - The absolute path of the device to be passed through in the device tree device_tree - absolute path of partial device tree in the Domain 0 irqs - interrupt number inside interrupt queue for the guest domain (see calculation steps below) iomem - the number of physical memory pages to be passed to the guest (see calculation steps below)
to calculate irqs corresponding to the guest domain, it needs to find the following line in PCIe settings described in xen.dts file:
iomem = [ "0xfd0e0,1", "0xfd480,1", "0xe0000,1000"] 1 page starting at "0xFD0E0000" base address of AXIPCIE_MAIN register (AXI to PCIe Bridge, Main Control and Status registers), 1 page starting at "0xFD480000" base address of PCIE_ATTRIB register (Register block that holds the attributes of the PCIe Controller, PCIe Attributes) and 1000 page starting at 0xe0000 base address for data.
Note that PCIe is mapped to multiple regions and it all needs to be on one single iomem line.